I dont use proteus for simulations; strictly Verilog and SPICE. But I think I have an idea what the problem might be.
I suspect the simulator is getting confused about the series resistors. When I model resistors in verilog, I usually use rtran statements [OK, technically it's tranif1 because I need to have a way to enable/disable the resistor]. But that becomes a problem when 2 or more resistors are in-series. In that case, I will model one of my resistors as either a pulldown or a pullup and fortunately that seems to work most of the time when I have resistors involved in a digital-only section of the design, such as a voltage-divider or a pullup resistor for a DIPswitch. So the resistor-model for digital simulations is basically open (default), weak pulldown, weak pullup, or rtran.
Of course, when it comes to modeling in SPICE, nothing needs to be done because that's a purely analog simulator.