7 digit nixie preliminary design

[Mitch]

This is my first attempt and before I go further, I would really appreciate critique and comments. This will never be a commercial product, just a platform for me to keep the mind working as I retire from application software development after many years. I mostly have the software running on an Arduinix multiplexed, but I want to directly drive the nixies for this project.

This is for the Z573M, of which I have many, and the Arduino Micro. If it works out, I'll modify the design to use the IN-18.

I intend to add RGB lighting, neon or LED colons, GPS, RTC, and whatever else I can think of. 

I started with Eagle, but because of board size limitations, I switched to Diptrace.

Thanks in advance.

[gregebert]

Thanks for mentioning the HV5522. I wasn't aware this device existed. Just be aware that VCC is nominally 12V, so you cant drive the inputs with TTL-level signals (you need a level-shifter). That shouldn't be a problem because you only need  4 or 5 signals from the Arduino. Going direct-drive is a wise choice, and you wont regret it.

I doubt the 10uA leakage current will be enough to cause unwanted glowing, but if you want to be extra paranoid then use the HV5530 with a higher voltage rating. Leakage tends to be proportional to the voltage-stress, so using a higher-rated device should result in less leakage. I suspect the manufacturer tests their devices > 300V, and the least-leaky ones are rated for 300V, whereas the leakier ones are rated 220V.

I can't tell what's inside the HV supply, so that's my only concern. There's a history of problems with HV supplies on this group. I prefer a voltage-doubler from the AC mains, which gets me +340VDC in the US. It wastes a bit of energy in the dropping resistors, but I dont use a transformer so that reduces the loss. You just have to be very careful with the design because it's NOT isolated.

[Mitch]

Thanks for your comments.

Checking the specs for the HV5522, the recommended operating voltage is 10.8-13.2. I'm working from part specs and schematics for several clocks that I own. The MOD-6 runs the HV5522 at 8v, the NixiChron runs at 5v to the HV5530, and the Spectrum 18, at 5v to the HV5522. I understand the purpose of a level shifter, but I don't know how to implement one. In any case, it appears that others run the chips reliably at lower voltages, so we'll see.

Regarding the power supply, that is the Tayloredge.com 1364. It is the same power supply used in the Mod-6. I've read about the difficulty in creating a stable design and that's way over my head, so I think the 1364 is the best way to go. 

I just ran out of pins, so time to buy Diptrace lite!

[gregebert]

I think you can get by with 4 control signals to the HV5522, so a quad op-amp will work as a level-shifter. Vcc for the op-amp and the HV5522/5530 can be the desired +12V. The "minus" input pin of each op-amp is set to 1/2 the logic-swing of the arduino, which probably uses 3.3V signalling. You can just use a resistor-divider. The "plus" inputs of the op-amp are driven directly from the arduino. The opamp outputs now swing the desired 0 to 12V.

Many opamps have internal compensation, so you probably wont need to worry about adding external compensation (to avoid ringing) as long as you keep your data-signal stable for several microseconds before and after active clk-edges. If you're making a PC board, you could leave a spot for a small cap between the opamp output and the 'minus' input and only add the cap if you observe excess ringing.

Using devices outside their datasheet-published range is asking for trouble; it might work, but it could be unreliable or erratic.

[John Rehwinkel]

> I think you can get by with 4 control signals to the HV5522, so a quad op-amp will work as a level-shifter.

That's using an op-amp as a comparator. This is generally not a good idea. Use a comparator instead.

> Using devices outside their datasheet-published range is asking for trouble; it might work, but it could be unreliable or erratic.

Bingo!

- John

[Quixotic Nixotic]

On 21 Apr 2015, at 20:08, John Rehwinkel wrote:

> That's using an op-amp as a comparator. This is generally not a good idea. Use a comparator instead.

In what way is using an op-amp comparator not using a comparator?

John S

[John Rehwinkel]

I think you can get by with 4 control signals to the HV5522, so a quad op-amp will work as a level-shifter.

That's using an op-amp as a comparator.  This is generally not a good idea.  Use a comparator instead.

In what way is using an op-amp comparator not using a comparator?

An op-amp and a comparator are two different (but related things).  An op-amp is designed to be operated closed-loop, with

its output somewhere between the supply rails.  A comparator is designed to be operated open-loop, with its output intended

to be at one rail or the other, switching rapidly between them.

While it is possible to use an op-amp as a comparator, it's not a good idea.  Some op-amps can latch up when used this way,

or take significant time to recover after being driven all the way to a rail.  It comes under the heading of using a device outside

of its data sheet ratings.

So when you ask "In what way is using an op-amp comparator not using a comparator?" I'm confused, as there is no such

animal as an "op-amp comparator", as far as I know.  Op-amps and comparators are two different (but related) things.

They both have positive and negative inputs and an output, and generally use the same triangular circuit symbol, but their

implementation and use are different.

For a detailed explanation of op-amps versus comparators, see this app note:

http://www.analog.com/media/en/technical-documentation/application-notes/AN-849.pdf

- John

[gregebert]

I had an unpleasant experience about 30 years ago (yeah, before the web existed and you had to use printed databooks...) with a comparator because I failed to read the datasheet correctly. I didn't realize it had an open-drain output, and I nearly went berserk trying to figure out why the bloody thing's output never went high. After adding a pullup resistor I got the output to go high, but it wasn't a nice sharp edge. Since my only source for parts at that time was Radio Shack, options were limited.

So I've stuck with opamps ever since. Not the best of excuses, but getting bit once was enough for me.

[John Rehwinkel]

I had an unpleasant experience about 30 years ago (yeah, before the web existed and you had to use printed databooks...) with a comparator because I failed to read the datasheet correctly. I didn't realize it had an open-drain output, and I nearly went berserk trying to figure out why the bloody thing's output never went high. After adding a pullup resistor I got the output to go high, but it wasn't a nice sharp edge.

Ah, the LM339!  I made the exact same mistake, about 18 years back.  I even wrote it up in my blog at the time:

http://madbodger.livejournal.com/75916.html

- John

[Mitch]

The attached data is for the LM339. It's called a comparator, but is it the best choice?

If I understand the formula correctly, if Vcc is +12v and Vin is +5v, a good value for Vref is around 4v. Using the formula, if Rref is 100 ohms than R1 should be 200 ohms. Five resistors are needed for each of the four comparators, for a total of twenty resistors. 

All four of the clock kits I have that use Supertex chips just run them on +5v, with no issues. Maybe this isn't worth the trouble.

Mitch

[Dekatron42]

CD4504B is a TTL->CMOS or CMOS->CMOS level translator: http://www.onsemi.com/pub_link/Collateral/MC14504B-D.PDF that works well in similar circuits and will probably work just fine here too. Maybe the CD40109B can be used in the reverse direction if needed: http://www.ti.com/lit/ds/symlink/cd40109b.pdf. Otherwise a few transistors and discrete components will work just fine too.

/Martin

[John Rehwinkel]

The attached data is for the LM339. It's called a comparator, but is it the best choice?

It's cheap and common, but not necessarily the best choice.  It has open collector outputs, so needs pull-up resistors.

If you use a TLC3704 or a MCP6544, you wouldn't need pull-ups.  However, if you're going to go buy chips anyway,

you may as well just buy a level shifter chip like a CD4504 or 74125 and dispense with all the comparators and resistors.

If I understand the formula correctly, if Vcc is +12v and Vin is +5v, a good value for Vref is around 4v.

I'd probably use 2 to 2.5V for Vref, that will work well with both CMOS and TTL outputs.

Using the formula, if Rref is 100 ohms than R1 should be 200 ohms. Five resistors are needed for each of the four comparators, for a total of twenty resistors.

First, you don't need the 1M resistor, you can omit that.  It gives some hysteresis, but with logic signals, it isn't needed.

Second, you just need to make Vref once, you can wire it to all four comparators.

You can probably dispense with the 10k series resistor as well, it's just to balance input currents.  In this case,

that doesn't matter.

That gets you down to six resistors (or two, if you use a comparator that doesn't need pull-ups).

I would use a much higher resistance for Rref, as 100 ohms will waste power.

Maybe go for 10k for Rref, then you could use 2k to get a 2V Vref.  Further, you can hook the high side of the reference voltage divider to +5V instead of +12V,

then use a pair of 10k resistors to get a 2.5V reference voltage.

All four of the clock kits I have that use Supertex chips just run them on +5v, with no issues. Maybe this isn't worth the trouble.

For a production circuit, it would make more sense, but for your own use, it's entirely up to you whether to bother.  If I were building

it, I'd just use a level shifter chip and be done with it.

- John

[Tobias]

When I was designing my clock I decided to run the uC at 3.3V since the gps and rf modules I wanted to use run at this voltage.

In order to communicate with the HV5522 I used a very simple bi-directional mosfet level shifter. I read about it on a app note and I use it since then. Although with the 5522 the link doesn't need to be bi-directional I just went with whatever I knew.

http://www.nxp.com/documents/application_note/AN10441.pdf

Best
Tobias

[chuck richards]

Wow. Thanks for that! It's so simple yet so
useful. That one got saved here for future reference! :)

Chuck

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[threeneurons]

Another reason for not using an op-amp, as a comparator, in this app, is speed. Op-amps are slew-rate limited by design. Some are faster than others, but most have added limiting circuitry. In this app, you're going to be piping a serial data stream, as fast as possible. Using common op-amps (LM324, TL084), you're not going to be able to stream faster than 10Kbpss. Maybe only 5Kbpss with the LM324.

For simplicity, I think the 4000 CMOS level shifters are the best option. Another option, is just using common emitter transistor stages. The pull-up, will be a simple resistor, so that will limit, your maximum speed. It should be good for a 100kbpss, or so, with 2.2K pull-ups, on the collectors. You can use the same value for the base current limiters. The logic phase will also, be inverted, but that can be compensated for, in software.

[Mitch]

Will the CD4104b be fast enough? It's available in a DIP package which works best here. Vcc connects to 5v, Vdd to 12v, SELECT is tied high, then it's just connecting in and out for each of the four signals. That's simple enough for me to deal with, and no resistors are needed.

[gregebert]

Make sure you pay close attention to the datasheet regarding power-sequencing. Many CMOS devices with multiple power supplies require them to be brought up (and down) in a specific order, otherwise internal damage will result.

You wouldn't believe all the effort we go to at my day-job not only to ensure correct power-sequencing, but also to identify all of the possible failure modes if sequencing is wrong.

[JohnK]

A similar 'nasty' can happen to experimenters - if multiple voltages are required on a board, don't 'common up' at the bench supplies with only  one common taken to the board. Lifting that common causes the 'total' voltage to distribute according to the various resistances - eg your 3V ICs could get most of the 12V IC's voltage.

[If you are new to electronics, try some calculations. OR just take my word for it.]

 

Which is also why I don't like multi-phase mains distribution in houses. Had to provide 'consultation' to a local hotel. The electrician put the damage down to a 'mains spike'. He had lifted the Neutral at the main switchboard as part of his RCD and compliance testing [he had added a new run]. This meant that the large airconditioner [high current] and the clocks/radios/tv/microwaves were in series across 415V line-to-line.

 

John K

Australia

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[Grahame Marsh]

On 23/04/2015 03:13, JohnK wrote:

A similar 'nasty' can happen to experimenters - if multiple voltages are required on a board, don't 'common up' at the bench supplies with only  one common taken to the board. Lifting that common causes the 'total' voltage to distribute according to the various resistances - eg your 3V ICs could get most of the 12V IC's voltage.

[If you are new to electronics, try some calculations. OR just take my word for it.]

 

John

Thanks for this warning. It makes complete sense the way you have descibed it (I'm not new to electronics but then I'm not a EE). My bench PSU is currently powering an experimental board using -12, +12 and +5V. Loss of the ground connection would not at all be good for the (expensive) 5V parts. But how to mitigate the risk? The PSU has a common ground so I have just run one ground wire to the board. I guess I must be doubly sure that the connection is secure before I power up and while I use the board. Also, I suppose I could put a 5V1 or 5V6 zener on the experimental board to try to clamp the drop across the 5V-to-ground at the board (cheap and reusable between experiments). Any other protection ideas would be good!

Grahame

[Dekatron42]

I use female banana jacks with wires soldered to the ground points and then connect them together if needed, I also use female banana jacks with wires soldered for the positive voltages - apart from not having a single failure ground point I get rid of all those pesky crocodile clips that fall off from time to time.

I also make use of the current limiting capabilities of my power supplies to make sure that they decrease the voltage if needed.

/Martin

[threeneurons]

Mouser has the 40109 in stock, in a 16 pin DIP ( 56 cents). Its not picky. Vcc can be greater than Vdd, or the other way around. In this case: Vcc = +5V, Vdd = +12V. At these voltages, I'd feel comfortable streaming upto ~1Mbps, maybe 1.5Mbps.

[threeneurons]

On Wednesday, April 22, 2015 at 9:56:59 AM UTC-7, threeneurons wrote:

... Another option, is just using common emitter transistor stages.

I threw this little circuit together, last night, and scoped it. Very good signals, on the scope, at 200KHz. I'm confident, it'll work as high as 500Kbps. 

 

[Alex]

On Thursday, 23 April 2015 03:14:11 UTC+1, johnk wrote:



A similar 'nasty' can happen to experimenters - if multiple voltages are required on a board, don't 'common up' at the bench supplies with only  one common taken to the board. Lifting that common causes the 'total' voltage to distribute according to the various resistances - eg your 3V ICs could get most of the 12V IC's voltage.

[If you are new to electronics, try some calculations. OR just take my word for it.]

 

Which is also why I don't like multi-phase mains distribution in houses. Had to provide 'consultation' to a local hotel. The electrician put the damage down to a 'mains spike'. He had lifted the Neutral at the main switchboard as part of his RCD and compliance testing [he had added a new run]. This meant that the large airconditioner [high current] and the clocks/radios/tv/microwaves were in series across 415V line-to-line.

 

John K

Australia

This is something I had never considered - lifted neutral on a 3 phase supply to a property which (like mine) has 3 single phase distribution boards (one on each phase) feeding different parts of the house (makes power cuts on individual phases interesting). Will bear that in mind. Could be nasty as one dist board has mainly water heating and other low ohmic loads on it (and a solar PV system for added complexity). 

On Wednesday, April 22, 2015 at 9:56:59 AM UTC-7, threeneurons wrote:

... Another option, is just using common emitter transistor stages. <snip schematic> I threw this little circuit together, last night, and scoped it. Very good signals, on the scope, at 200KHz. I'm confident, it'll work as high as 500Kbps. 

Would that AC bypass cap on the input not skew the input signal / add phase shift depending on long sequences of 1s or 0s? What is its hidden purpose?

[John Rehwinkel]

> This is something I had never considered - lifted neutral on a 3 phase supply to a property which (like mine) has 3 single phase distribution boards (one on each phase) feeding different parts of the house (makes power cuts on individual phases interesting). Will bear that in mind. Could be nasty as one dist board has mainly water heating and other low ohmic loads on it (and a solar PV system for added complexity).

We lost a phase at a place I used to live once, so I turned on a couple of electric stove burners to bridge some power from the live phase to the dead one, so I could run the lights on the dead phase (at reduced voltage, but enough to see by).

> Would that AC bypass cap on the input not skew the input signal / add phase shift depending on long sequences of 1s or 0s? What is its hidden purpose?

It’s basically a feed-forward capacitor, giving extra current to turn the transistor on and off faster when the level changes. The rest of the time (your long
sequences of 0s and 1s) it’s effectively out of circuit, and the base resistor provides enough drive to keep the transistor at its current state.

- John

[Mitch]

I think the 4109 is the best way to go for this project.

Regarding clock speed, th HV5122 accepts data at up to 8MHz. The uC runs at 16MHz. I'm not sure how many clock cycles it take to send each bit, but I doubt that it could reach 1MHz so the 4109 should be good even clocking at full uC speed. The refresh display refresh rate will be 100 milliseconds, but that will increase when fades and effects are added, probably to around 10-20 milliseconds.

I'll update the schematic shortly.

[gregebert]

Plan on using 2 I/O write-cycles to send a bit. This way you will guarantee setup and hold-time margin at the receiving end assuming the receiver captures on rising-edges of clk. For example:

cycle A: data bit 1, clk=0

cycle B: data bit 1, clk=1

cycle A: data bit 2, clk=0

cycle B: data bit 2, clk=1

I use this sequence in my big clock which has a 96-bit shift register (72 bits for hours and minutes hand info), and it's clocked at 200nsec (5Mhz). Despite having a 3 foot-long clock line (yes, it's properly terminated), there are no observable bit errors. BTW, I use an FPGA programmed in Verilog, not a CPU.

[GastonP]

Sweeeeeeet! Can you share a little more about this? Which FPGA? Why not a CPU? Schematics and/or Verilog :D

[gregebert]

On Saturday, April 25, 2015 at 6:42:09 PM UTC-7, GastonP wrote:

Sweeeeeeet! Can you share a little more about this? Which FPGA? Why not a CPU? Schematics and/or Verilog :D

I use an Altera Cyclone II with 4500 logic elements. You can get assembled boards on Ebay for about $20US.

Altera's software is free, and very high quality.

I didn't use a CPU because all operations must be serialized or time-sliced. With an FPGA, it's digital gates so things can be done concurrently if you wish. Also, I do a lot of chip design work for my day job, so I live, eat, sleep, stink, think, and drink Verilog. I have considered putting a Z80 CPU on the FPGA and using software, but I can easily do it in hardware. Also, verilog is usable for both design and simulation, so it reduces the number of tools I have to use.

The verilog source code wont be of any use without the schematics and other documentation. I can provide a pdf copy of the design report on request, but I dont have time to provide any support. One PCB has been in operation over 2 years now, and I'm building a second one with green neon bulbs and a magic-eye tube in the center, but no surrounding digits. Now, if someone has some spare NIMO tubes I'd be happy to provide you a assembled & working board in exchange for 20 NIMO tubes (yeah I'm dreaming....)

[Mitch]

Noted. Thanks.

Schematic is mostly finished. If anyone has a moment to look it over and comment, I'd appreciate it. 

[Mitch]

The boards arrived from OSH Park a few days ago. First I built and tested the power supply, then the display logic and tubes. Never having designed a pc board using DipTrace or even a schematic more involved than a few parts, I was amazed that this thing actually works. I spent about an hour writing a test program that serially sends 74 bits to the three, HV5530PJ chips. I thought about using separate clock and data pins for the 1/10 seconds HV5530 while designing because I was concerned about sending too much serial data, but that doesn't appear to be necessary. The display updates easily at 100ms and probably at 10ms too, but that's too fast to observe just by looking at the Nixies.

The only issue I have at the moment is how to dim the Nixies. I thought that using PWM on the blanking input of the HV5530 would work, but it does not. The Taylor edge power supply documentation warns against using the HV enable line for that purpose, so I'm stuck. Any suggestions? I think the Nixiechron uses PWM on the HV enable line, but that clock uses a custom power supply. I'll check to see how the MOD-6 does it because it too uses the Taylor supply, and a Supertex Nixie driver.

Next up is to take the Arduinix software I wrote and replace the multiplex drivers with programming appropriate for this direct drive project. Then to install the MCP23017 port expander and the RTC chip, and programming. Also included on the board for future development are a light sensor, although without dimming it may not be of much use, a motion sensor, RGB LED lighting, and GPS. Hopefully reading and parsing the GPS data can be done between 1/10 second display updates.

Here are some problems I found so far, in addition those above:

Piezo buzzer is on pin 13, which is also the on-board LED. It buzzes when downloading. This is a simple fix with just a cut trace and a wire to one of the two unused pins on the Arduino.

Supercap is too close to the HV5530 socket so it will have to be angled.

RGB LED and transistor patterns are much too small. Easy to work around, but fixed next revision.

Nixie pattern diameter is too large.

Dimming??

Many, many adjustments to the silk screen.

Adjustments to parts placement here and there.

That's about it. I originally wanted a software playground with many hardware options since I outgrew the Arduinix, and so far I'm pleased with what I have. We'll see where it goes. I still plan to do an IN-18 version at some point soon after all the hardware on this board is up and running.

Mitch

[gregebert]

Nice board.

I'm curious why the blanking pin on the HV5530 isn't working. Is it that you dont see any dimming, or is it something else ? Be careful about the setting of the POL pin; if it's at the wrong level you will turn on all cathodes when you attempt to blank the displays.

I'm working on a 14-tube IN-18 clock that uses the HV5530, and I plan to use the blanking pin for dimming. My control logic is entirely FPGA, so I have no issues about software timing, etc.

Although it's inefficient, you could implement a lower-speed PWM by sending alternate serial packets with all cathodes off, then the desired cathodes on, etc. I dont know if your CPU can handle that workload under software control, though.

The datasheet parameters dont specify a minimum propagation delay on the DataOut pin (tDLH), and there is a minimum hold-time requirement on the DataIn pin, so it's theoretically not possible to cascade these devices unless you  alternately invert the CLK signal or add delay on the DataIn pin. This wont cause a problem with blanking, but it could cause marginal operation. I chose to alternately invert the CLK signal.

[Mitch]

Thanks for your comments.

POL is grounded, and serial bits are sent low to light a segment. Using analogWrite(blankPin, 200); to enable PWM, most or all segments of all Nixies will light. I think sending alternate serial packets will suck too much CPU.

I grounded POL following the Nixiechron schematic. Somehow dimming works well with that clock. Hopefully the answer is not to connect POL to VCC. Traces are under the PLCC socket. 

I don't understand the part about inverting CLK. All of this came from a pile of Nixie clock schematics. That is beyond the limit of my knowledge.

[gregebert]

According to my read of the datasheet, POL needs to be high in order for blanking to extinguish all cathodes. That also would explain why sending a '0' to the HV5530 will cause a cathode to illuminate. So, if you have POL low you will be attempting to turn-on all cathodes at the same time. The power supply is probably current-limited so it would prevent all cathodes from actually glowing.

Regarding the CLK, the inversion of every-other clk-input is way to guarantee hold-time is satisfied when shift registers are cascaded, at the expense of setup time. Basically, the sending device transmits on the falling-edge of clk, and the receiving device samples on the rising-edge (because of the added inverter). You have a guaranteed hold-margin of 1/2 clk cycle.

[Mitch]

Thank you again. Tomorrow I'll move POL from VSS to VDD on all three chips, from the top of the sockets. No other way. Hopefully that will do, since the display seems to update comfortably at better than 100ms so there is no apparent issue with timing. I don't think it's worth the time to investigate calculating the exact timing, at least not yet. Adding two CMOS, 12v inverters between CLK on the three chips would require another IC. Hopefully that won't be necessary. 

I'll post an update shortly.  And I really do appreciate the help and advice. I was at a dead end with this issue.

[David Forbes]

Mitch,

Those of us who have been laying out PC boards for many years have
learned (the hard way) that it's a good idea to route all inputs that
are tied to Gnd or Vcc on the bottom layer with a narrow trace, so that
it may be easily cut later when we discover that the board design had an
error.

Not that circuit designers ever make mistakes.

I can tell you how to cut a trace that's buried in layer 4 of a 12 layer
board, using a drill bit and a microscope and an ohmmeter. Because I've
had to do it.

On 6/10/15 5:21 PM, Mitch wrote:
>
> I grounded POL following the Nixiechron schematic. Somehow dimming works
> well with that clock. Hopefully the answer is not to connect POL to VCC.
> Traces are under the PLCC socket.
>

--
David Forbes, Tucson AZ

[Mitch]

Thanks Gregebert, and thanks David. I removed the pin from the PLCC socket and soldered a thin wire directly to Vdd and to the POL pin on the HV5530. I hated to do that!

Dimming now works perfectly.

David, I will do a revision 2 of the board, and I'll try to arrange GND and Vcc on the bottom. Thanks for the suggestion.

Now to bring up more of the hardware. I'll be back.