Verilog Meetup project status as of 2025-08-23
Yuri Panchul
Verilog Meetup project status as of 2025-08-23
Yuri Panchul
The current activities: book, manual, seminars in California, seminars internationally, board support etc:
One-liners:
Writing a textbook “Information Technology Architectures” with Purdue University.
Writing an FPGA lab manual for the high school students.
Creating an open-source UVM AXI-Lite Verification IP for educational purposes.
An idea of an event at CalPoly San Luis Obispo: uArch, foss ASIC and DV.
An idea of a similar event in UC Santa Cruz.
Report about Verilog Meetup / Mirai event in Mexico.
Preparing for the Maker Faire event in Vallejo, California on September 26-28.
Creating the board support packages for four boards that use Gowin, Altera and Xilinx.
BSP for Kiwi (Vietnam) Gowin boards, as well as OrangePi MSOC board.
Need to find an owner for the Lattice board support.
A demo for the Maker Faire: Tang Nano 9K + a Geiger counter.
A demo for the Make Faire: Tang Nano 4K + a camera within BGM example infra.
A regional seminar in Bosnia + Serbia, Croatia, Montenegro.
An idea of a regional seminar in Kenya.
Online-based platform for systemverilog-homework.
Formal verification methodology that can be added to the educational project.
In details:
Writing a textbook “Information Technology Architectures” with Purdue University - Dmitry Gusev, Yuri Panchul. This textbook is aimed at freshmen students to introduce them to the whole technology stack, including gates, RTL, microarchitecture, CPU, assembly programming, high-level languages, operating systems and networking. The chapters on combinational and sequential logic have references to the Verilog Meetup examples. Status: in progress, delayed.
Writing an FPGA lab manual for the high school students, hobbyists and other beginners with Jim Burnham. The manual is based on a restricted board set and simplified examples to make it more accessible. The manual has to be self-sufficient: each chapter has to include a minimal necessary theory and a step-by-step instruction to run the examples on the board. Status: uncertain. The original plan was to finish it during the summer; whether Jim cam work on it during the school year is unclear.
Creating an open-source UVM AXI-Lite Verification IP for educational purposes, based on non-UVM VIP by Yuri Panchul and UVM testbench by Shiva Swaroop.
https://github.com/verilog-meetup/non-uvm-axi-lite-verification-ipEntertaining the idea by Stanley To of making events at CalPoly San Luis Obispo on FPGA and ASIC design: introductory FPGA hackathon, microarchitectural topics, open-source ASIC design and verification. After discussing this idea with Stanley I also got an idea to make a session called “The Limits of AI in SystemVerilog Microarchitecture” based on the SystemVerilog microarchitecture challenge for AI No.2. Adding the flow control. https://github.com/verilog-meetup/systemverilog-microarchitecture-challenge-for-ai-2 - and the follow-up challenges. Status: pending the discussion at CalPoly.
Starting the discussion to make the same type of seminars at the University of California Santa Cruz. Status: The idea has been expressed to UCSC students Ethan James and (? forgot the name). Pending on their talk with their professor.
Report about Verilog Meetup / Mirai event in Mexico. Jorge Zavala put some information about it on Facebook and LinkedIn, but i want him to add an article to verilog-meetup.com website. Note to pictures to articles in WordPress you need to shrink them to 2000 pixels side max before uploading to a WordPress website. If someone volunteers he can prepare an article - this is a good practice to learn how to write WordPress posts:
https://www.facebook.com/zavala55/posts/pfbid02ASDQVhjHcBMNksksh1DpZJb7gjzUn65T4vAiWNEXjZVxMARRZL5wfwcpAwKHBuhwl
https://www.linkedin.com/feed/update/urn:li:activity:7364760694992338944/
https://www.linkedin.com/feed/update/urn:li:activity:7362145908592922625/
https://youtu.be/MYHOxDsbEGc?si=r_LFgfeEjo8cOo4cPreparing for the Maker Faire event in Vallejo, California on September 26-28.
https://bayarea.makerfaire.com/
Previous year - https://makerfaire.com/maker/entry/75973/
Things to do:
1) Design and order the tablecloth similar to the poster on OpenSauce.
2) Order 500 or 1000 business cards.
3) Solder 50 FPGA board kits - need help from Ramprakash Baskar and other volunteers.
4) Add the materials to the Maker Faire website.Creating the board support packages for four boards:
1) ChipInventor ChipBoard v2.2 - https://chipinventor.com/boards.html
2) MAX1000 Altera MAX10 FPGA Development Board - https://www.aliexpress.us/item/2255801025932658.html
3) Digilent Cmod A7-35T
4) Digilent Cmod S7
Status: assigned: Asher Wrobel with the help regarding the ChipInventor board from Professor Aroca from Wernher Von Braun Labs.Creating more board support packages, particularly for a new line of Gowin boards called Kiwi from Vietnam - might be useful to connect with the community in Vietnam:
https://onekiwi.com.vn/products/
https://onekiwi.com.vn/products/kiwi-1p5-fpga-board/
We can ask Matt Stankus to work on them. In addition, Matt can assemble and test the support forthe OrangePi MSOC board. The support was created by Vadim Ostrikov, but has to be independently evaluated:
https://github.com/verilog-meetup/basics-graphics-music/tree/main/boards/orangepi_msoc
The board - https://www.aliexpress.us/item/3256808533233771.htmlNeed to find an owner for the Lattice board support - Jiang ZC? Some Lattice boards are supported now using Yosys-based toolchain ( https://github.com/YosysHQ/oss-cad-suite-build ) but:
1) We need to have local demos for the 7 boards I have and
2) Somebody has to evaluate Lattice's proprietary tools with the examples in basics-graphics-music.Creating a demo for the Maker Faire that integrates Tang Nano 9K board with a Geiger counter. Using an existing dem with Terasic DE10-Lite as a baseline example. Status: assigned to Asher Wrobel.
Create a demo for the Make Faire that integrates Tang Nano 4K board with a camera within basic-graphics-music (BGM) example infrastructure. Status: assigned to Dan Barrowman.
A regional seminar in Bosnia with the surrounding countries: Serbia, Croatia, Montenegro. Status: the idea was developed with Jasmin at chili-chips.com, however it was put on hold due to a lack of sponsors and content clarity. This idea can be resurrected. Action item: make a Zoom call with Jasmin at least 2 weeks before the Maker Faire event, facilitate Jasmin’s participation in the Maker Faire event to rehearse the introductory part of the potential event.
A regional seminar in Kenya in connection with Philip Sisa. Status: The idea has been discussed with a university in Kenya and is pending marketing evaluation of the seminar's usefulness for local students. The local students do some outsourcing of microcontroller programming for foreign countries, design some PCB boards and work locally in system designs like food dispensing machines and industrial automation.
Boards designed in Kenya - https://www.waziup.org/iot-edge-platform/#boardsOnline-based platform for systemverilog-homework developed by Viacheslav Gomolko. Action item: make a call with him to evaluate his integration of microarchitectural exercises.
Formal verification methodology that can be added to the educational project, developed by Alexander Gnusin. Action item: make a call with him to evaluate.
A note on all board support packages: a board support package makes sense if and only if:
You implement support for pretty much all examples and basic peripherals, i.e. cover buttons, LEDs, 7-segment display, LCD/VGA/HDMI/whatever graphics, a microphone and a sound output.
If you implement only the first example with buttons and LEDs and give it to me to continue, I will not accept it because you are just giving me additional work: I would have to study and probably fix your design before adding all the other code in the BSP. This might be more labor-intensive than doing it from scratch.In general, there should not be any ad-hoc changes in the script names that make the board look different from any other 40 or so boards in basics-graphics-music. By adding your own script or a makefile you give me additional work to do the same things for the other 40 boards. Such things should be discussed beforehand.
Similarly, there should not be unusual pin arrangements that make the board look different from any other 40 or so boards in basics-graphics-music and cause a “What?” reaction. A user should expect all boards with similar interfaces (such as Pmod) to be interchangeable in the lab. The user experience should be consistent.
If you come up with the “let’s rewrite all bash scripts to Python” idea, please make sure to implement it for all 40+ boards and toolchains (Xilinx, Altera, Gowin, Lattice etc). Demoing it for a single or a couple of boards is an another way of creating additional work for other people or splitting the project into two making it confusing for the users.
No AI-generated code in the repository. The purpose of this project is to train you how to write Verilog or work with the toolchains, not to manage me cleaning up your AI output.
Whether you are participating in a specific project or just learn RTL or DV, the general recommendations are:
If you study Verilog from scratch, read Chapter 4 in Harris & Harris, in parallel with running basics-graphics-music examples on an FPGA board, in parallel with doing SystemVerilog Homework exercises.
If you prefer to ignore reading the basics-graphics-music (BGM) example instruction and just run the vendor’s GUI and start asking the questions why something does not work - I cannot help you to troubleshoot such problems because the scripts in BGM were created specifically with the purpose to isolate a user from the vendor-specific details.
Same thing for using the vendor’s example instead of the recommended BGM. Helping to troubleshoot errors when using the vendor’s examples just creates additional work for both me and you. And those efforts are in an unimportant area instead of focusing on what matters - your design functionality, microarchitecture, timing etc. It also makes the experience board and vendor-specific.If you need to prepare for a job interview, make sure to run the microarchitectural part of systemverilog-homework exercises, as well as the new series of SV challenges for AI (those are good for humans as well as for AI):
If you want to contribute to the exercises, work on a board-support package or on a new microarchitecture, verification IP or CPU-related example, let’s discuss it.
Thank you,
Yuri Panchul
Daniel Barrowman
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Eugene Wang
Sent: Sunday, August 24, 2025 8:39:34 AM
To: Yuri Panchul <yu...@panchul.com>
Cc: mee...@googlegroups.com <mee...@googlegroups.com>
Subject: Re: [meetsv] Verilog Meetup project status as of 2025-08-23