Hi,
I can't say for sure, but it may be PRU pins that are being described?
If you take a look at the following file:
you can find some of these pins. For example:
P9_27_PRU="147" P9_27_GPIO="115" P9_27_PIN="gpio" P9_27_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin" P9_27_INFO="gpio3_19 default gpio3_19 gpio3_19 gpio3_19 gpio3_19 eqep0b_in pru0_out5 pru0_in5" P9_27_CAPE=""
or
P9_25_PRU="149" P9_25_GPIO="117" P9_25_PIN="audio" P9_25_PINMUX="default gpio gpio_pu gpio_pd gpio_input qep pruout pruin" P9_25_INFO="gpio3_21 default gpio3_21 gpio3_21 gpio3_21 gpio3_21 eqep0_strobe pru0_out7 pru0_in7" P9_25_CAPE=""
|
|
147 here is linked to 9_27, and 149 to 9_25
|
I see in the novamill hal file I found online (your link did not work), Pin 142, 143, 144, 145, 149... are used which would correspond to pins 42,43, 44... on the P8, and these would be in the LCD pinout region on the bus.
Generally these pins are reserved for the LCD, so my guess is that the number 149 does not refer to pin 49 of P8, rather a different numbering scheme, perhaps like the one I mention above.
Jeff