Anyone been using (Mesa) hostmot2 spi (spi, bspi, dbspi) cores on Machinekit ?

67 views
Skip to first unread message

Michael Brown

unread,
May 30, 2019, 8:29:04 PM5/30/19
to Machinekit
MK-Hal:
I expect the answer to be no as while implementing this functionality on the mksocfpoga DExx_Cramps I had to iron out some noticable bugs:
I expect to upstream these changes soon (in machinekit-hal), however they will probably
break any (work arounded) exsisting implementations, that will need to be updated:

Also I added support for the buffered spi's with decoded chip selects (dbspi). (tested to work ok)

MkSoCFPGA:
Lastly I had a problem with 3 spi messages being send instead of one:
The issue here relates to All quartus based mksocfpga configs:
as the uio port was set to clock out data for 2+ cycles to the hm2 cores.
This meant that all data writes to the hm2 cores where trippled,(not a huge issue for the cores used up to date)
 first notacable via the bspi cores that then sent same message 2 times more when write triggered.

So here is the nessesary Global change, of the write timing:

Everything is tested on my (3) DExx_Cramps based machines, and all works fine here,,, 

Best wishes
Michael B.

Bas de Bruijn

unread,
May 31, 2019, 5:58:38 AM5/31/19
to Michael Brown, Machinekit
Hi Michael,

I have your image and a de0 nano with 2 of Charles’ DB25 breakout boards. So I would think that changing pins so we get one DB25 board and other functions on the second header will be easy.

I’m happy to test this when I’ve soldered the ic to a breakout board. (Got a lot of exercise soldering the 2 boards)

Here’s a pic of the de0 nano with 2 db25 boards and 3 7i76 boards.
image1.jpeg

How would you work with i2c? Got these too https://www.adafruit.com/product/1083

Cheers,
Bas 

Michael Brown

unread,
May 31, 2019, 12:04:24 PM5/31/19
to Machinekit


On Friday, 31 May 2019 11:58:38 UTC+2, Bas de Bruijn wrote:
well I found this web page:

then created (attached) i2c_dbspi.comp 
a scaled down version of the mesa_7i65.comp:

measured the outputs of clk (red) and data (blue)on my scope screen  shots (attached) also:

    //hm2_dbspi_setup_chan(name, chan, cs, bits, mhz, delay(ns), cpol, cpha, noclear, noecho, samplelate)
    r = hm2_dbspi_setup_chan(name,    0,  0,     9,      3,              0,     0,       0,           0,           1, 0);

    //hm2_dbspi_setup_chan(name, chan, cs, bits, mhz, delay(ns), cpol, cpha, noclear, noecho, samplelate)
    r = hm2_dbspi_setup_chan(name,    0,  0,     9,      3,              0,     0,       1,           0,          1, 0);

    //hm2_dbspi_setup_chan(name, chan, cs, bits, mhz, delay(ns), cpol, cpha, noclear, noecho, samplelate)
    r = hm2_dbspi_setup_chan(name,    0,  0,     9,      3,             0,      1,       0,           0,          1, 0);

    //hm2_dbspi_setup_chan(name, chan, cs, bits, mhz, delay(ns), cpol, cpha, noclear, noecho, samplelate)
    r = hm2_dbspi_setup_chan(name,    0,  0,     9,      3,             0,      1,       1,          0,           1, 0);

The data is unfortunately locked to the rising or falling edge of the clock (perhaps spoiling the setup time):
The last variation is whats comes closest to fullfilling the requirements on the web page:

bspi_9-bit_cpol-1_cpha_1.png


START is when SCL is HI, SDA goes to HI->LO.

STOP is when SCL is HI and SDA goes LO->HI.


It may work however...

 
Cheers,
Bas 
bspi_9-bit_cpol-1_cpha_0.png
bspi_9-bit_cpol-1_cpha_1.png
bspi_9-bit_cpol-0_cpha_0.png
bspi_9-bit_cpol-0_cpha_1.png
i2c_dbspi.comp

Michael Brown

unread,
May 31, 2019, 1:32:29 PM5/31/19
to Machinekit
Reply all
Reply to author
Forward
0 new messages