[PATCH 0/4] sunxi: R40: Enable USB and Ethernet

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Andre Przywara

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Jan 1, 2020, 6:45:08 PM1/1/20
to Jagan Teki, Maxime Ripard, Chen-Yu Tsai, u-b...@lists.denx.de, linux...@googlegroups.com
This series enables the USB ports on boards with the Allwinner R40 SoC,
also updates the Bananapi M2 Berry board support.
Patch 1/4 updates the M2 Berry .dts file, so that we get the USB and
Ethernet nodes that we need to enable Ethernet in patch 2/4.
Patch 3/4 adds support for the USB PHY in the R40 SoC, so that the final
patch can enable USB for the two R40 boards that U-Boot supports.

Tested on the Bananapi M2 Berry. I don't have the M2 Ultra, but USB
should work there with this series too. Ethernet was already enabled.

Cheers,
Andre.

Andre Przywara (4):
sunxi: dts: R40: Update Bananapi M2 Berry .dts
sunxi: defconfig: Bananapi M2 Berry: enable Ethernet
phy: sun4i-usb: Add Allwinner R40 support
sunxi: defconfig: R40 boards: enable USB

arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts | 135 ++++++++++++++++++++++++---
arch/arm/mach-sunxi/Kconfig | 1 +
configs/Bananapi_M2_Ultra_defconfig | 4 +
configs/bananapi_m2_berry_defconfig | 6 ++
drivers/phy/allwinner/phy-sun4i-usb.c | 12 +++
5 files changed, 143 insertions(+), 15 deletions(-)

--
2.14.5

Andre Przywara

unread,
Jan 1, 2020, 6:45:09 PM1/1/20
to Jagan Teki, Maxime Ripard, Chen-Yu Tsai, u-b...@lists.denx.de, linux...@googlegroups.com
Update the .dts file from the kernel, which carries much more nodes,
some of them we need to enable USB and Ethernet support for the board.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
---
arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts | 135 ++++++++++++++++++++++++---
1 file changed, 120 insertions(+), 15 deletions(-)

diff --git a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
index 54ad4db468..15c22b06fc 100644
--- a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
+++ b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -50,6 +50,7 @@
compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40";

aliases {
+ ethernet0 = &gmac;
serial0 = &uart0;
};

@@ -57,6 +58,17 @@
stdout-path = "serial0:115200n8";
};

+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";

@@ -84,12 +96,18 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
+ clocks = <&ccu CLK_OUTA>;
+ clock-names = "ext_clock";
};
};

&ahci {
- phy-supply = <&reg_eldo3>; /* VDD12-SATA */
- ahci-supply = <&reg_dldo4>; /* VDD25-SATA */
+ ahci-supply = <&reg_dldo4>;
+ phy-supply = <&reg_eldo3>;
+ status = "okay";
+};
+
+&de {
status = "okay";
};

@@ -98,6 +116,32 @@
status = "okay";
};

+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_rgmii_pins>;
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii";
+ phy-supply = <&reg_dc1sw>;
+ status = "okay";
+};
+
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
status = "okay";

@@ -111,6 +155,41 @@

#include "axp22x.dtsi"

+&mmc0 {
+ vmmc-supply = <&reg_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pg_pins>;
+ vmmc-supply = <&reg_dldo2>;
+ vqmmc-supply = <&reg_dldo1>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&pio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk_out_a_pin>;
+ vcc-pa-supply = <&reg_aldo2>;
+ vcc-pc-supply = <&reg_dcdc1>;
+ vcc-pd-supply = <&reg_dcdc1>;
+ vcc-pe-supply = <&reg_eldo1>;
+ vcc-pf-supply = <&reg_dcdc1>;
+ vcc-pg-supply = <&reg_dldo1>;
+};
+
+&reg_aldo2 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vcc-pa";
+};
+
&reg_aldo3 {
regulator-always-on;
regulator-min-microvolt = <2700000>;
@@ -118,6 +197,12 @@
regulator-name = "avcc";
};

+&reg_dc1sw {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-gmac-phy";
+};
+
&reg_dcdc1 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
@@ -152,12 +237,27 @@
regulator-name = "vcc-wifi-io";
};

+/*
+ * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same
+ * time, with the two being in sync, to be able to meet maximum power
+ * consumption during transmits. Since this is not really supported
+ * right now, just use the two as always on, and we will fix it later.
+ */
+
&reg_dldo2 {
+ regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi";
};

+&reg_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+};
+
&reg_dldo4 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
@@ -170,28 +270,33 @@
regulator-name = "vdd1v2-sata";
};

-&mmc0 {
- vmmc-supply = <&reg_dcdc1>;
- bus-width = <4>;
- cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */
+&tcon_tv0 {
status = "okay";
};

-&mmc1 {
+&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pg_pins>;
- vmmc-supply = <&reg_dldo2>;
- vqmmc-supply = <&reg_dldo1>;
- mmc-pwrseq = <&wifi_pwrseq>;
- bus-width = <4>;
- non-removable;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

-&uart0 {
+&uart3 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pb_pins>;
+ pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>;
+ uart-has-rtscts;
status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&ccu CLK_OUTA>;
+ clock-names = "lpo";
+ vbat-supply = <&reg_dldo2>;
+ vddio-supply = <&reg_dldo1>;
+ device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
+ /* TODO host wake line connected to PMIC GPIO pins */
+ shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */
+ max-speed = <1500000>;
+ };
};

&usbphy {
--
2.14.5

Andre Przywara

unread,
Jan 1, 2020, 6:45:09 PM1/1/20
to Jagan Teki, Maxime Ripard, Chen-Yu Tsai, u-b...@lists.denx.de, linux...@googlegroups.com
The M2 Berry features the normal Gigabit PHY connected to the SoC's MAC,
so enable the sun8i-emac driver to support Ethernet on the board.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
---
configs/bananapi_m2_berry_defconfig | 2 ++
1 file changed, 2 insertions(+)

diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig
index a5b8632ef6..a97be06188 100644
--- a/configs/bananapi_m2_berry_defconfig
+++ b/configs/bananapi_m2_berry_defconfig
@@ -15,3 +15,5 @@ CONFIG_SCSI_AHCI=y
CONFIG_AXP_DLDO4_VOLT=2500
CONFIG_AXP_ELDO3_VOLT=1200
CONFIG_SCSI=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_RGMII=y
--
2.14.5

Andre Przywara

unread,
Jan 1, 2020, 6:45:11 PM1/1/20
to Jagan Teki, Maxime Ripard, Chen-Yu Tsai, u-b...@lists.denx.de, linux...@googlegroups.com
Now that the USB PHY on the Allwinner R40 SoC is supported, enable USB
support for the two R40 boards U-Boot supports.
For this we need to add the GPIO pin that powers the USB port(s), also
enable the usual suspects (OHCI/EHCI support).

Signed-off-by: Andre Przywara <andre.p...@arm.com>
---
configs/Bananapi_M2_Ultra_defconfig | 4 ++++
configs/bananapi_m2_berry_defconfig | 4 ++++
2 files changed, 8 insertions(+)

diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig
index 7a30dd7f7f..bbf931329c 100644
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@@ -19,4 +19,8 @@ CONFIG_SUN8I_EMAC=y
CONFIG_AXP_DLDO4_VOLT=2500
CONFIG_AXP_ELDO3_VOLT=1200
CONFIG_SCSI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB1_VBUS_PIN="PH23"
+CONFIG_USB2_VBUS_PIN="PH23"
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig
index a97be06188..654974e47d 100644
--- a/configs/bananapi_m2_berry_defconfig
+++ b/configs/bananapi_m2_berry_defconfig
@@ -17,3 +17,7 @@ CONFIG_AXP_ELDO3_VOLT=1200
CONFIG_SCSI=y
CONFIG_SUN8I_EMAC=y
CONFIG_RGMII=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB1_VBUS_PIN="PH23"
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
--
2.14.5

Andre Przywara

unread,
Jan 1, 2020, 6:45:11 PM1/1/20
to Jagan Teki, Maxime Ripard, Chen-Yu Tsai, u-b...@lists.denx.de, linux...@googlegroups.com
Since every Allwinner USB PHY seems to be slightly different from each
other, we need to add the compatible string and the respective data
structure to make it work on the R40/V40 SoC.
Nothing spectacular this time, just one less USB controller than the H3.
Copied from the Linux kernel.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
---
arch/arm/mach-sunxi/Kconfig | 1 +
drivers/phy/allwinner/phy-sun4i-usb.c | 12 ++++++++++++
2 files changed, 13 insertions(+)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 16d41b83af..3a3b673430 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -250,6 +250,7 @@ config MACH_SUN8I_R40
select SUPPORT_SPL
select SUNXI_DRAM_DW
select SUNXI_DRAM_DW_32BIT
+ select PHY_SUN4I_USB

config MACH_SUN8I_V3S
bool "sun8i (Allwinner V3s)"
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 5e8f87717f..f7309057b9 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -73,6 +73,7 @@ enum sun4i_usb_phy_type {
sun8i_a33_phy,
sun8i_a83t_phy,
sun8i_h3_phy,
+ sun8i_r40_phy,
sun8i_v3s_phy,
sun50i_a64_phy,
sun50i_h6_phy,
@@ -571,6 +572,16 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
.phy0_dual_route = true,
};

+static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
+ .num_phys = 3,
+ .type = sun8i_r40_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A33,
+ .dedicated_clocks = true,
+ .enable_pmu_unk1 = true,
+ .phy0_dual_route = true,
+};
+
static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
.num_phys = 1,
.type = sun8i_v3s_phy,
@@ -611,6 +622,7 @@ static const struct udevice_id sun4i_usb_phy_ids[] = {
{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = (ulong)&sun8i_a33_cfg },
{ .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
+ { .compatible = "allwinner,sun8i-r40-usb-phy", .data = (ulong)&sun8i_r40_cfg },
{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
{ .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg},
--
2.14.5

Jagan Teki

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Jan 21, 2020, 3:35:42 AM1/21/20
to Andre Przywara, Maxime Ripard, Chen-Yu Tsai, U-Boot-Denx, linux-sunxi
On Thu, Jan 2, 2020 at 5:15 AM Andre Przywara <andre.p...@arm.com> wrote:
>
> Update the .dts file from the kernel, which carries much more nodes,
> some of them we need to enable USB and Ethernet support for the board.
>
> Signed-off-by: Andre Przywara <andre.p...@arm.com>
> ---

Would be better to have all R40 files to sync at the same time?

Jagan Teki

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Jan 24, 2020, 12:47:27 PM1/24/20
to Andre Przywara, Maxime Ripard, Chen-Yu Tsai, U-Boot-Denx, linux-sunxi
On Thu, Jan 2, 2020 at 5:15 AM Andre Przywara <andre.p...@arm.com> wrote:
>
Applied all to u-boot-sunxi/master
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