[PATCH 1/7] arm64: dts: allwinner: h6: Add clock to CPU cores

[Clément Péron]

From: Yangtao Li <tiny....@gmail.com>

The ARM CPU cores are fed by the CPU clock from the CCU. Add a
reference to the clock for each CPU core, along with the clock
transition latency.

Signed-off-by: Yangtao Li <tiny....@gmail.com>
Signed-off-by: Clément Péron <peron...@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 3329283e38ab..aef4ae760d5e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -25,6 +25,8 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};

cpu1: cpu@1 {
@@ -32,6 +34,8 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};

cpu2: cpu@2 {
@@ -39,6 +43,8 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};

cpu3: cpu@3 {
@@ -46,6 +52,8 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
};
};

--
2.20.1

[Clément Péron]

Hi Sunxi maintainers and members,

Now that required drivers are merged we can contibute on DVFS support for
Allwinner H6.

This serie is based on Yangtao Li serie[0] and Megous works[1].

Most of the OPP tables are taken from original vendor kernel[2].
Plus there is a new CPU frequency @1.8GHz.

I wrote a simple script to randomly set a frequency during a random time[3].
With this script and using stress-ng during a day I didn't see any issue.
Moreover I have tested specifically the 1.8GHz on my Beelink GS1, max thermal
80°C is reached after ~10min and then the SoC oscillates quickly between 1.5
and 1.8GHz.

I also test that that offlining CPU0 and doing DVFS on other CPUs works.
As CPU regulator is only set for CPU0.

But maybe it doesn't cost much to set the regulator for all the CPUs?

Jernej test the GPU devfreq on several H6 board particulary the Tanix TX6 which
doesn't have a proper dedicated PMIC and doesn't had any trouble with it.

Do you think I can enable GPU OPP for all H6 Boards?

Also Yangtao Li enable DVFS for OrangePi and Pine64, as I can't test them I
didn't reenable these boards. Please, let me know if you want me to add these
boards in this serie.

Thanks,
Clément

0: https://patchwork.kernel.org/cover/10815117/
1: https://megous.com/git/linux/log/?h=ths-5.7
2: https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi#L345-L517
3: https://gist.github.com/clementperon/55a055dae3f13bbd14fb39c0069fe2e2

Clément Péron (4):
arm64: dts: allwinner: h6: set thermal polling time
arm64: dts: allwinner: h6: Add GPU Operating Performance Points table
arm64: configs: Enable sun50i cpufreq nvmem
arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Beelink
GS1

Ondrej Jirman (2):
arm64: dts: allwinner: h6: Add thermal trip points/cooling map
arm64: dts: allwinner: h6: Add CPU Operating Performance Points table

Yangtao Li (1):
arm64: dts: allwinner: h6: Add clock to CPU cores

.../dts/allwinner/sun50i-h6-beelink-gs1.dts | 10 +-
.../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 103 ++++++++++++++++++
.../boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi | 74 +++++++++++++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 44 +++++++-
arch/arm64/configs/defconfig | 1 +
5 files changed, 226 insertions(+), 6 deletions(-)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi

--
2.20.1

[Clément Péron]

From: Ondrej Jirman <meg...@megous.com>

This enables passive cooling by down-regulating CPU voltage
and frequency.

Signed-off-by: Ondrej Jirman <meg...@megous.com>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 24 ++++++++++++++++++++
1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index aef4ae760d5e..d4d3963705f5 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -908,6 +908,30 @@
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 0>;
+
+ trips {
+ cpu_hot_trip: cpu-hot {
+ temperature = <80000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_very_hot_trip: cpu-very-hot {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu-hot-limit {
+ trip = <&cpu_hot_trip>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};

gpu-thermal {
--
2.20.1

[Clément Péron]

Add reasonable thermal polling time for Allwinner H6.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index d4d3963705f5..c3e4f09f60ce 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -905,8 +905,8 @@

thermal-zones {
cpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
+ polling-delay-passive = <100>;
+ polling-delay = <1000>;
thermal-sensors = <&ths 0>;

trips {
@@ -935,8 +935,8 @@
};

gpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
+ polling-delay-passive = <100>;
+ polling-delay = <1000>;
thermal-sensors = <&ths 1>;
};
};
--
2.20.1

[Clément Péron]

From: Ondrej Jirman <meg...@megous.com>

Add an Operating Performance Points table for the CPU cores to
enable Dynamic Voltage & Frequency Scaling on the H6.

Signed-off-by: Ondrej Jirman <meg...@megous.com>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

.../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 103 ++++++++++++++++++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 +
2 files changed, 107 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
new file mode 100644
index 000000000000..b480c33f426b
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Ondrej Jirman <meg...@megous.com>
+// Copyright (C) 2020 Clément Péron <peron...@gmail.com>
+
+/ {
+ cpu0_opp_table: opp_table0 {
+ compatible = "allwinner,sun50i-h6-operating-points";
+ nvmem-cells = <&speedbin_efuse>;
+ opp-shared;
+
+ opp@480000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <480000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@720000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <720000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@816000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <816000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@888000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <888000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@1080000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <1080000000>;
+
+ opp-microvolt-speed0 = <940000>;
+ opp-microvolt-speed1 = <880000>;
+ opp-microvolt-speed2 = <880000>;
+ };
+
+ opp@1320000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <1320000000>;
+
+ opp-microvolt-speed0 = <1000000>;
+ opp-microvolt-speed1 = <940000>;
+ opp-microvolt-speed2 = <940000>;
+ };
+
+ opp@1488000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <1488000000>;
+
+ opp-microvolt-speed0 = <1060000>;
+ opp-microvolt-speed1 = <1000000>;
+ opp-microvolt-speed2 = <1000000>;
+ };
+
+ opp@1800000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <1800000000>;
+
+ opp-microvolt-speed0 = <1160000>;
+ opp-microvolt-speed1 = <1100000>;
+ opp-microvolt-speed2 = <1100000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index c3e4f09f60ce..a9304fec245c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -253,6 +253,10 @@
#address-cells = <1>;
#size-cells = <1>;

+ speedbin_efuse: speed@1c {
+ reg = <0x1c 0x4>;
+ };
+
ths_calibration: thermal-sensor-calibration@14 {
reg = <0x14 0x8>;
};
--
2.20.1

[Clément Péron]

Add an Operating Performance Points table for the GPU to

enable Dynamic Voltage & Frequency Scaling on the H6.

Signed-off-by: Clément Péron <peron...@gmail.com>
---
.../boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi | 74 +++++++++++++++++++
1 file changed, 74 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi
new file mode 100644
index 000000000000..4a1814844fe0
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi
@@ -0,0 +1,74 @@

+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

+// Copyright (C) 2020 Clément Péron <peron...@gmail.com>
+
+/ {

+ gpu_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+
+ opp@756000000 {
+ opp-hz = /bits/ 64 <756000000>;
+ opp-microvolt = <1040000>;
+ };
+ opp@624000000 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-microvolt = <950000>;
+ };
+ opp@576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-microvolt = <930000>;
+ };
+ opp@540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ opp-microvolt = <910000>;
+ };
+ opp@504000000 {
+ opp-hz = /bits/ 64 <504000000>;
+ opp-microvolt = <890000>;
+ };
+ opp@456000000 {
+ opp-hz = /bits/ 64 <456000000>;
+ opp-microvolt = <870000>;
+ };
+ opp@432000000 {
+ opp-hz = /bits/ 64 <432000000>;
+ opp-microvolt = <860000>;
+ };
+ opp@420000000 {
+ opp-hz = /bits/ 64 <420000000>;
+ opp-microvolt = <850000>;
+ };
+ opp@408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <840000>;
+ };
+ opp@384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt = <830000>;
+ };
+ opp@360000000 {
+ opp-hz = /bits/ 64 <360000000>;
+ opp-microvolt = <820000>;
+ };
+ opp@336000000 {
+ opp-hz = /bits/ 64 <336000000>;
+ opp-microvolt = <810000>;
+ };
+ opp@312000000 {
+ opp-hz = /bits/ 64 <312000000>;
+ opp-microvolt = <810000>;
+ };
+ opp@264000000 {
+ opp-hz = /bits/ 64 <264000000>;
+ opp-microvolt = <810000>;
+ };
+ opp@216000000 {
+ opp-hz = /bits/ 64 <216000000>;
+ opp-microvolt = <810000>;
+ };
+ };
+};
+
+&gpu {
+ operating-points-v2 = <&gpu_opp_table>;

+ #cooling-cells = <2>;
+};

--
2.20.1

[Clément Péron]

Allwinner H6 needs this driver to be able to get
the correct speed_bin required for DVFS.

Enable this option in arm64 defconfig.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 4db223dbc549..28b25fc0347c 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -83,6 +83,7 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPUFREQ_DT=y
CONFIG_ACPI_CPPC_CPUFREQ=m
+CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
CONFIG_ARM_SCPI_CPUFREQ=y
CONFIG_ARM_IMX_CPUFREQ_DT=m
--
2.20.1

[Clément Péron]

Enable CPU and GPU opp tables for Beelink GS1.

This needs also to change the CPU regulator min/max voltage to fit
the OPP table.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

.../arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index df6d872c34e2..8e65d56a7c85 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -4,6 +4,8 @@
/dts-v1/;

#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
+#include "sun50i-h6-gpu-opp.dtsi"

#include <dt-bindings/gpio/gpio.h>

@@ -70,6 +72,10 @@
};
};

+&cpu0 {
+ cpu-supply = <&reg_dcdca>;
+};
+
&de {
status = "okay";
};
@@ -226,8 +232,8 @@

reg_dcdca: dcdca {
regulator-always-on;
- regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1080000>;
+ regulator-min-microvolt = <820000>;
+ regulator-max-microvolt = <1160000>;
regulator-name = "vdd-cpu";
};

--
2.20.1

[Ondřej Jirman]

Hello,

On Sun, Apr 05, 2020 at 12:49:09PM +0200, Clément Péron wrote:
> Add reasonable thermal polling time for Allwinner H6.
>
> Signed-off-by: Clément Péron <peron...@gmail.com>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index d4d3963705f5..c3e4f09f60ce 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -905,8 +905,8 @@
>
> thermal-zones {
> cpu-thermal {
> - polling-delay-passive = <0>;
> - polling-delay = <0>;
> + polling-delay-passive = <100>;
> + polling-delay = <1000>;
> thermal-sensors = <&ths 0>;

This is not necessary, and will not do anything useful, since the driver
uses interrupts to update the thermal zone's temperature. Please keep the
values at 0.

With your settings the thermal zone would just add a polling timer in addition
to being updated every 250ms via THS interrupt. The real thermal measurements
are available every 250ms anyway, so setting a smaller period here will not do
anything useful, and 1s period will not lead to slower updates either.

Values of 0 mean tell the thermal zone to rely on thermal driver to update
the thermal zone by itself (via interrupt) and to not poll.

regards,
o.

> trips {
> @@ -935,8 +935,8 @@
> };
>
> gpu-thermal {
> - polling-delay-passive = <0>;
> - polling-delay = <0>;
> + polling-delay-passive = <100>;
> + polling-delay = <1000>;
> thermal-sensors = <&ths 1>;
> };
> };
> --
> 2.20.1
>

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[Ondřej Jirman]

Hello,

The H6 datasheet says:

- VDD-CPU Power Supply for CPU 0.81 - 1.08 V (recommended)
- VDD-CPU Power Supply for CPU -0.30 - 1.30 V (abs max)

So I guess there's no need to increase the lower limit, because it matches
the datasheet already.

regards,
o.

> regulator-name = "vdd-cpu";
> };
>
> --
> 2.20.1
>

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[Ondřej Jirman]

Hello Clément,

On Sun, Apr 05, 2020 at 12:49:06PM +0200, Clément Péron wrote:
> Hi Sunxi maintainers and members,
>
> Now that required drivers are merged we can contibute on DVFS support for
> Allwinner H6.
>
> This serie is based on Yangtao Li serie[0] and Megous works[1].
>
> Most of the OPP tables are taken from original vendor kernel[2].
> Plus there is a new CPU frequency @1.8GHz.
>
> I wrote a simple script to randomly set a frequency during a random time[3].
> With this script and using stress-ng during a day I didn't see any issue.
> Moreover I have tested specifically the 1.8GHz on my Beelink GS1, max thermal
> 80°C is reached after ~10min and then the SoC oscillates quickly between 1.5
> and 1.8GHz.

Thank you for working on this. :) I wonder what SoC bin you tested this on.

I have a patch to print it here:

https://megous.com/git/linux/commit/?h=ths-5.7&id=c5ddd2a45c7e04dcec31619b58de7c798ad6594c

> I also test that that offlining CPU0 and doing DVFS on other CPUs works.
> As CPU regulator is only set for CPU0.
>
> But maybe it doesn't cost much to set the regulator for all the CPUs?
>
> Jernej test the GPU devfreq on several H6 board particulary the Tanix TX6 which
> doesn't have a proper dedicated PMIC and doesn't had any trouble with it.
>
> Do you think I can enable GPU OPP for all H6 Boards?
>
> Also Yangtao Li enable DVFS for OrangePi and Pine64, as I can't test them I
> didn't reenable these boards. Please, let me know if you want me to add these
> boards in this serie.

Feel free to add these OPPs also to OrangePi 3 dts, I've been running mine with
this OPP table for at least a year already (I have the worst SoC bin).

Though I'll run a bit more comprehensive test for more frequencies, like you
did, just to be sure.

One thing I wonder about is if there should not be some small ramp delay on the
CPU regulator node, because voltage change probably takes some small time to
apply, compared to changing the PLL frequency. And I have no idea if the CPU
is not running for some very small time out of spec during transitions.

I didn't find timing information in the PMIC datasheet, but I suppose based
on the DCDCA frequency of 3MHz that it will adapt to the new voltage in the
range of 1s-10s of microseconds.

In datasheet of the similar PMIC (AXP813) there is this note:

DVM (Dynamic Voltage scaling Management) ramp rate: 2.5mV/us at buck frequency 3MHz

I think it will be simiar with AXP805.

regards,
o.

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[Clément Péron]

Hi Ondřej,

On Sun, 5 Apr 2020 at 13:51, Ondřej Jirman <meg...@megous.com> wrote:
>
> Hello Clément,
>
> On Sun, Apr 05, 2020 at 12:49:06PM +0200, Clément Péron wrote:
> > Hi Sunxi maintainers and members,
> >
> > Now that required drivers are merged we can contibute on DVFS support for
> > Allwinner H6.
> >
> > This serie is based on Yangtao Li serie[0] and Megous works[1].
> >
> > Most of the OPP tables are taken from original vendor kernel[2].
> > Plus there is a new CPU frequency @1.8GHz.
> >
> > I wrote a simple script to randomly set a frequency during a random time[3].
> > With this script and using stress-ng during a day I didn't see any issue.
> > Moreover I have tested specifically the 1.8GHz on my Beelink GS1, max thermal
> > 80°C is reached after ~10min and then the SoC oscillates quickly between 1.5
> > and 1.8GHz.
>
> Thank you for working on this. :) I wonder what SoC bin you tested this on.
>
> I have a patch to print it here:
>
> https://megous.com/git/linux/commit/?h=ths-5.7&id=c5ddd2a45c7e04dcec31619b58de7c798ad6594c

My SoC bin is :
[ 0.584553] sun50i_cpufreq_nvmem: Using CPU speed bin speed0

>
> > I also test that that offlining CPU0 and doing DVFS on other CPUs works.
> > As CPU regulator is only set for CPU0.
> >
> > But maybe it doesn't cost much to set the regulator for all the CPUs?
> >
> > Jernej test the GPU devfreq on several H6 board particulary the Tanix TX6 which
> > doesn't have a proper dedicated PMIC and doesn't had any trouble with it.
> >
> > Do you think I can enable GPU OPP for all H6 Boards?
> >
> > Also Yangtao Li enable DVFS for OrangePi and Pine64, as I can't test them I
> > didn't reenable these boards. Please, let me know if you want me to add these
> > boards in this serie.
>
> Feel free to add these OPPs also to OrangePi 3 dts, I've been running mine with
> this OPP table for at least a year already (I have the worst SoC bin).
>
> Though I'll run a bit more comprehensive test for more frequencies, like you
> did, just to be sure.
>
> One thing I wonder about is if there should not be some small ramp delay on the
> CPU regulator node, because voltage change probably takes some small time to
> apply, compared to changing the PLL frequency. And I have no idea if the CPU
> is not running for some very small time out of spec during transitions.
>
> I didn't find timing information in the PMIC datasheet, but I suppose based
> on the DCDCA frequency of 3MHz that it will adapt to the new voltage in the
> range of 1s-10s of microseconds.
>
> In datasheet of the similar PMIC (AXP813) there is this note:
>
> DVM (Dynamic Voltage scaling Management) ramp rate: 2.5mV/us at buck frequency 3MHz

Good point, this information should be added for both CPU and GPU regulator.
This could be nice to confirm this point with a scope.

Also I remark that Allwinner user higher temperature than what we set :
alarm_low_temp = <105000>;
alarm_high_temp = <110000>;
alarm_temp_hysteresis = <15000>;
shut_temp= <115000>;
https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi#L1924

Don't you think that we can push a bit higher the temperature it's
actually at 80°C ?

Thanks for the review,
Clement

[Clément Péron]

Hi Ondřej,

Thanks for the explanations,
I will drop this patch.

Regards,
Clément

[Ondřej Jirman]

Hi,

On Sun, Apr 05, 2020 at 04:33:37PM +0200, Clément Péron wrote:
> Hi Ondřej,

[ ... ]

> Good point, this information should be added for both CPU and GPU regulator.
> This could be nice to confirm this point with a scope.
>
> Also I remark that Allwinner user higher temperature than what we set :
> alarm_low_temp = <105000>;
> alarm_high_temp = <110000>;
> alarm_temp_hysteresis = <15000>;
> shut_temp= <115000>;
> https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi#L1924
>
> Don't you think that we can push a bit higher the temperature it's
> actually at 80°C ?

We probably can. But just 5°C between high temp and criticla temp is probably
not enough. I'd probably set our value to something like 90-100°C so that quick
temperature spike before regulation kicks in would not shutdown the CPU.

regards,
o.

[Clément Péron]

Hi,

OK I will push it to 85°C and leave the critical to 100°C.

Test it again and will send a v2

Regards,
Clément

[Clément Péron]

Hi,

On Sun, 5 Apr 2020 at 12:49, Clément Péron <peron...@gmail.com> wrote:
>
> Hi Sunxi maintainers and members,
>
> Now that required drivers are merged we can contibute on DVFS support for
> Allwinner H6.
>
> This serie is based on Yangtao Li serie[0] and Megous works[1].
>
> Most of the OPP tables are taken from original vendor kernel[2].
> Plus there is a new CPU frequency @1.8GHz.
>
> I wrote a simple script to randomly set a frequency during a random time[3].
> With this script and using stress-ng during a day I didn't see any issue.
> Moreover I have tested specifically the 1.8GHz on my Beelink GS1, max thermal
> 80°C is reached after ~10min and then the SoC oscillates quickly between 1.5
> and 1.8GHz.

This result is wrong ignore it.

I will resend new one in next serie.

Regards,
Clement

[Clément Péron]

Hi Sunxi maintainers and members,

Now that required drivers are merged we can contibute on DVFS
support for Allwinner H6.

This serie is based on Yangtao Li serie[0] and Ondřej Jirman work[1].

Most of the OPP tables are taken from original vendor kernel[2].

Plus there is a new CPU frequencies at 1.6GHz, 1.7GHz and 1.8GHz.

I wrote a simple script to randomly set a frequency during
a random time[3].

With this script and using stress-ng during several hours, I didn't

see any issue. Moreover I have tested specifically the 1.8GHz on my

Beelink GS1, max thermal 85°C is reached very quickly and then the
SoC oscillates quickly between 1.5 and 1.8GHz. So i have added
1.6GHz and 1.7GHz my board now oscillate slower between 1.5GHz and
1.6GHz swapping every second and temperature is also morestable.

I also test that that offlining CPU0 and doing DVFS on other CPUs
works. As CPU regulator is only set for CPU0.

But maybe it doesn't cost much to set the regulator for all the CPUs?

Jernej test the GPU devfreq on several H6 board particulary the
Tanix TX6 which doesn't have a proper dedicated PMIC and doesn't
had any trouble with it.

Do you think I can enable GPU OPP for all H6 Boards?

Also Yangtao Li enable DVFS for Pine64, as I can't test it.
I'm waiting for his ack or someone who has a Pine64 and can test this
serie before reenabling this board.

Thanks,
Clément

0: https://patchwork.kernel.org/cover/10815117/
1: https://megous.com/git/linux/log/?h=ths-5.7
2: https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi#L345-L517
3: https://gist.github.com/clementperon/55a055dae3f13bbd14fb39c0069fe2e2

Changes since v1 (thanks to Ondřej Jirman):
- Remove Polling thermal
- Add Orange Pi boards
- Remove minimal voltage change for Beelink GS1
- Add ramp-deplay for GPU and CPU regulators
- Push to thermal point to 85°C (Allwinner set them to 100°C and 115°C)
- Added 1.6GHz and 1.7GHz to OPP table.

Clément Péron (4):

arm64: dts: allwinner: h6: Add GPU Operating Performance Points table
arm64: configs: Enable sun50i cpufreq nvmem
arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Beelink
GS1

arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Orange Pi
boards

Ondrej Jirman (2):
arm64: dts: allwinner: h6: Add thermal trip points/cooling map
arm64: dts: allwinner: h6: Add CPU Operating Performance Points table

Yangtao Li (1):
arm64: dts: allwinner: h6: Add clock to CPU cores

.../dts/allwinner/sun50i-h6-beelink-gs1.dts | 10 +-

.../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 121 ++++++++++++++++++
.../boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi | 74 +++++++++++
.../dts/allwinner/sun50i-h6-orangepi.dtsi | 10 +-
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 36 ++++++
arch/arm64/configs/defconfig | 1 +
6 files changed, 250 insertions(+), 2 deletions(-)

[Clément Péron]

From: Yangtao Li <tiny....@gmail.com>

The ARM CPU cores are fed by the CPU clock from the CCU. Add a
reference to the clock for each CPU core, along with the clock
transition latency.

Signed-off-by: Yangtao Li <tiny....@gmail.com>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 3329283e38ab..aef4ae760d5e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi

@@ -25,6 +25,8 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;

+ clock-latency-ns = <244144>; /* 8 32k periods */

};

cpu1: cpu@1 {
@@ -32,6 +34,8 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;

+ clock-latency-ns = <244144>; /* 8 32k periods */

};

cpu2: cpu@2 {
@@ -39,6 +43,8 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;

+ clock-latency-ns = <244144>; /* 8 32k periods */

};

cpu3: cpu@3 {
@@ -46,6 +52,8 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;

+ clock-latency-ns = <244144>; /* 8 32k periods */

};
};

--
2.20.1

[Clément Péron]

From: Ondrej Jirman <meg...@megous.com>

This enables passive cooling by down-regulating CPU voltage
and frequency.

Signed-off-by: Ondrej Jirman <meg...@megous.com>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 24 ++++++++++++++++++++
1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index aef4ae760d5e..e0dd0757be0b 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi

@@ -908,6 +908,30 @@
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 0>;
+
+ trips {
+ cpu_hot_trip: cpu-hot {

+ temperature = <85000>;

[Clément Péron]

From: Ondrej Jirman <meg...@megous.com>

Add an Operating Performance Points table for the CPU cores to

enable Dynamic Voltage & Frequency Scaling on the H6.

Signed-off-by: Ondrej Jirman <meg...@megous.com>
Signed-off-by: Clément Péron <peron...@gmail.com>
---

.../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 121 ++++++++++++++++++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 +
2 files changed, 125 insertions(+)

create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi

new file mode 100644
index 000000000000..8c1e413c6af9
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
@@ -0,0 +1,121 @@

+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

+// Copyright (C) 2020 Ondrej Jirman <meg...@megous.com>

+// Copyright (C) 2020 Clément Péron <peron...@gmail.com>
+
+/ {

+ cpu0_opp_table: opp_table0 {
+ compatible = "allwinner,sun50i-h6-operating-points";
+ nvmem-cells = <&speedbin_efuse>;
+ opp-shared;
+
+ opp@480000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <480000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@720000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <720000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@816000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <816000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@888000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <888000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@1080000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <1080000000>;
+
+ opp-microvolt-speed0 = <940000>;
+ opp-microvolt-speed1 = <880000>;
+ opp-microvolt-speed2 = <880000>;
+ };
+
+ opp@1320000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <1320000000>;
+
+ opp-microvolt-speed0 = <1000000>;
+ opp-microvolt-speed1 = <940000>;
+ opp-microvolt-speed2 = <940000>;
+ };
+
+ opp@1488000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <1488000000>;
+
+ opp-microvolt-speed0 = <1060000>;
+ opp-microvolt-speed1 = <1000000>;
+ opp-microvolt-speed2 = <1000000>;
+ };
+

+ opp@1608000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <1608000000>;
+
+ opp-microvolt-speed0 = <1090000>;
+ opp-microvolt-speed1 = <1030000>;
+ opp-microvolt-speed2 = <1030000>;
+ };
+
+ opp@1704000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <1704000000>;
+
+ opp-microvolt-speed0 = <1120000>;
+ opp-microvolt-speed1 = <1060000>;
+ opp-microvolt-speed2 = <1060000>;
+ };
+
+ opp@1800000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <1800000000>;
+
+ opp-microvolt-speed0 = <1160000>;
+ opp-microvolt-speed1 = <1100000>;
+ opp-microvolt-speed2 = <1100000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu0_opp_table>;

+ #cooling-cells = <2>;
+};

+
+&cpu1 {
+ operating-points-v2 = <&cpu0_opp_table>;

+ #cooling-cells = <2>;
+};

+
+&cpu2 {
+ operating-points-v2 = <&cpu0_opp_table>;

+ #cooling-cells = <2>;
+};

+
+&cpu3 {
+ operating-points-v2 = <&cpu0_opp_table>;

+ #cooling-cells = <2>;
+};

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index e0dd0757be0b..6b7af858614a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi

[Clément Péron]

Add an Operating Performance Points table for the GPU to

enable Dynamic Voltage & Frequency Scaling on the H6.

Signed-off-by: Clément Péron <peron...@gmail.com>
---
.../boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi | 74 +++++++++++++++++++
1 file changed, 74 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi

new file mode 100644

index 000000000000..4a1814844fe0
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi

@@ -0,0 +1,74 @@

+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

+// Copyright (C) 2020 Clément Péron <peron...@gmail.com>
+
+/ {

+ #cooling-cells = <2>;
+};

--
2.20.1

[Clément Péron]

Allwinner H6 needs this driver to be able to get
the correct speed_bin required for DVFS.

Enable this option in arm64 defconfig.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

[Clément Péron]

Enable CPU and GPU opp tables for Beelink GS1.

This needs to change the CPU regulator max voltage to fit
the OPP table.

Also add the ramp-delay information to avoid any out of spec
running as the regulator is slower at reaching the voltage
requested compare to the PLL reaching the frequency.

There is no such information for AXP805 but similar PMIC (AXP813)
has a DVM (Dynamic Voltage scaling Management) ramp rate equal
to 2500uV/us.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

.../arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index df6d872c34e2..d76a0dd75222 100644

--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -4,6 +4,8 @@
/dts-v1/;

#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
+#include "sun50i-h6-gpu-opp.dtsi"

#include <dt-bindings/gpio/gpio.h>

@@ -70,6 +72,10 @@
};
};

+&cpu0 {
+ cpu-supply = <&reg_dcdca>;
+};
+
&de {
status = "okay";
};

@@ -227,7 +233,8 @@
reg_dcdca: dcdca {
regulator-always-on;

regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1080000>;

+ regulator-max-microvolt = <1160000>;
+ regulator-ramp-delay = <2500>;
regulator-name = "vdd-cpu";
};

@@ -235,6 +242,7 @@
regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
+ regulator-ramp-delay = <2500>;
regulator-name = "vdd-gpu";
};

--
2.20.1

[Clément Péron]

Enable CPU and GPU opp tables for Orange Pi boards.

This needs to change the CPU regulator max voltage to fit
the OPP table.

Also add the ramp-delay information to avoid any out of spec
running as the regulator is slower at reaching the voltage
requested compare to the PLL reaching the frequency.

There is no such information for AXP805 but similar PMIC (AXP813)
has a DVM (Dynamic Voltage scaling Management) ramp rate equal
to 2500uV/us.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 10 +++++++++-

1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
index 37f4c57597d4..f3ba500ce4c6 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
@@ -5,6 +5,8 @@

/dts-v1/;

#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
+#include "sun50i-h6-gpu-opp.dtsi"

#include <dt-bindings/gpio/gpio.h>

@@ -45,6 +47,10 @@

};
};

+&cpu0 {
+ cpu-supply = <&reg_dcdca>;
+};
+

&ehci0 {
status = "okay";
};
@@ -161,7 +167,8 @@

reg_dcdca: dcdca {
regulator-always-on;
regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1080000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-ramp-delay = <2500>;
regulator-name = "vdd-cpu";
};

@@ -169,6 +176,7 @@

[Clément Péron]

Hi Maxime,

On Mon, 6 Apr 2020 at 10:16, Maxime Ripard <max...@cerno.tech> wrote:

>
> On Sun, Apr 05, 2020 at 07:35:58PM +0200, Clément Péron wrote:
> > Add an Operating Performance Points table for the GPU to
> > enable Dynamic Voltage & Frequency Scaling on the H6.
> >
> > Signed-off-by: Clément Péron <peron...@gmail.com>
> > ---
> > .../boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi | 74 +++++++++++++++++++
> > 1 file changed, 74 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi
> > new file mode 100644
> > index 000000000000..4a1814844fe0
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi
> > @@ -0,0 +1,74 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +// Copyright (C) 2020 Clément Péron <peron...@gmail.com>
> > +
> > +/ {
> > + gpu_opp_table: opp_table1 {
>

> A node name is supposed to be a generic description, so what about
> using gpu-opp-table (and cpu-opp-table) instead?

>
> > + compatible = "operating-points-v2";
> > +
> > + opp@756000000 {
> > + opp-hz = /bits/ 64 <756000000>;
> > + opp-microvolt = <1040000>;
> > + };
> > + opp@624000000 {
> > + opp-hz = /bits/ 64 <624000000>;
> > + opp-microvolt = <950000>;
> > + };
>

> Ordering by ascending frequency would be great here.
Indeed will fix it.

>
> Also, why did you need to create a new DTSI for it? Is there some
> downside to enabling it for all the users?

I didn't want to enable it for all boards as I can't test them and not all board
have a dedicated regulator for VDD-GPU.
Hence my question in the cover,
But with Jernej Škrabec test on Tanix TX6 I think it can be safely
enable on all boards.

Regards,
Clement

>
> Maxime

[Clément Péron]

Hi Maxime,

On Mon, 6 Apr 2020 at 10:10, Maxime Ripard <max...@cerno.tech> wrote:
>
> Hi,

>
> On Sun, Apr 05, 2020 at 07:35:54PM +0200, Clément Péron wrote:
> > Now that required drivers are merged we can contibute on DVFS
> > support for Allwinner H6.
> >
> > This serie is based on Yangtao Li serie[0] and Ondřej Jirman work[1].
> >
> > Most of the OPP tables are taken from original vendor kernel[2].
> > Plus there is a new CPU frequencies at 1.6GHz, 1.7GHz and 1.8GHz.
> >
> > I wrote a simple script to randomly set a frequency during
> > a random time[3].
>

> If you ever need to do that ever again, cpufreq-ljt-stress-test (found
> here https://github.com/ssvb/cpuburn-arm) has proven to be very
> reliable to detect cpufreq related issues. stress-ng might not be
> enough since the (at least older) Allwinner SoCs tend to create cache
> corruption when undervolted, and that might not be unnoticed by
> stress-ng but will be catched by cpufreq-ljt-stress-test.

Thanks for the tool and explanation. I will test the v3 with this one.

>
> Also, it will test each frequency, while random frequencies might skip
> a few.

I didn't count them but there was more than 2000lines, probability to miss
a frequency is really low. Also changing from 500MHz to 1.8GHz could have
trigger some out-of-spec issue.

But just to be sure I will add an init phase before doing random stuff.

>
> > With this script and using stress-ng during several hours, I didn't
> > see any issue. Moreover I have tested specifically the 1.8GHz on my
> > Beelink GS1, max thermal 85°C is reached very quickly and then the
> > SoC oscillates quickly between 1.5 and 1.8GHz. So i have added
> > 1.6GHz and 1.7GHz my board now oscillate slower between 1.5GHz and
> > 1.6GHz swapping every second and temperature is also morestable.
> >
> > I also test that that offlining CPU0 and doing DVFS on other CPUs
> > works. As CPU regulator is only set for CPU0.
> >
> > But maybe it doesn't cost much to set the regulator for all the CPUs?
> >
> > Jernej test the GPU devfreq on several H6 board particulary the
> > Tanix TX6 which doesn't have a proper dedicated PMIC and doesn't
> > had any trouble with it.
> >
> > Do you think I can enable GPU OPP for all H6 Boards?
>

> It seems you're doing it?
No I don't, see my answer on patch 4/7.

Thanks for your review,
Clément

>
> Maxime

[Clément Péron]

Hi,

On Sun, 5 Apr 2020 at 19:36, Clément Péron <peron...@gmail.com> wrote:
>
> Enable CPU and GPU opp tables for Orange Pi boards.
>
> This needs to change the CPU regulator max voltage to fit
> the OPP table.
>
> Also add the ramp-delay information to avoid any out of spec
> running as the regulator is slower at reaching the voltage
> requested compare to the PLL reaching the frequency.
>
> There is no such information for AXP805 but similar PMIC (AXP813)
> has a DVM (Dynamic Voltage scaling Management) ramp rate equal
> to 2500uV/us.
>
> Signed-off-by: Clément Péron <peron...@gmail.com>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
> index 37f4c57597d4..f3ba500ce4c6 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi

Made a mistake here.
Ondrej Jirman test DVFS on Orange Pi 3 board which is not this device-tree file.

Will fix in V3.

Regards,
Clément

[Clément Péron]

Hi,

On Mon, 6 Apr 2020 at 10:14, Maxime Ripard <max...@cerno.tech> wrote:

>
> On Sun, Apr 05, 2020 at 07:35:57PM +0200, Clément Péron wrote:
> > From: Ondrej Jirman <meg...@megous.com>
> >
> > Add an Operating Performance Points table for the CPU cores to
> > enable Dynamic Voltage & Frequency Scaling on the H6.
> >
> > Signed-off-by: Ondrej Jirman <meg...@megous.com>
> > Signed-off-by: Clément Péron <peron...@gmail.com>
> > ---
> > .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 121 ++++++++++++++++++
> > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 +
> > 2 files changed, 125 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
> > new file mode 100644
> > index 000000000000..8c1e413c6af9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +// Copyright (C) 2020 Ondrej Jirman <meg...@megous.com>
> > +// Copyright (C) 2020 Clément Péron <peron...@gmail.com>
> > +
> > +/ {
> > + cpu0_opp_table: opp_table0 {
>

> Node names shouldn't have an underscore, this will trigger a DTC
> warning.

>
> > + compatible = "allwinner,sun50i-h6-operating-points";
> > + nvmem-cells = <&speedbin_efuse>;
> > + opp-shared;
> > +
> > + opp@480000000 {
> > + clock-latency-ns = <244144>; /* 8 32k periods */
> > + opp-hz = /bits/ 64 <480000000>;
> > +
> > + opp-microvolt-speed0 = <880000>;
> > + opp-microvolt-speed1 = <820000>;
> > + opp-microvolt-speed2 = <820000>;
> > + };
>

> And similarly, if you have a unit-address (the part after @), you
> should have a matching reg property. You should use a dash instead.

> You should order this by address, so after the THS calibration. Also,
> using a less generic node name than "speed" would be great. What about
> soc-bin ?

Indeed it's too generic.
I will keep coherency with i.MX8 and use "cpu_speed_grade"

Thanks for the review,
Clement

>

> Maxime

[Clément Péron]

Hi Maxime,

On Mon, 6 Apr 2020 at 11:07, Clément Péron <peron...@gmail.com> wrote:
>
> Hi Maxime,
>
> On Mon, 6 Apr 2020 at 10:10, Maxime Ripard <max...@cerno.tech> wrote:
> >
> > Hi,
> >
> > On Sun, Apr 05, 2020 at 07:35:54PM +0200, Clément Péron wrote:
> > > Now that required drivers are merged we can contibute on DVFS
> > > support for Allwinner H6.
> > >
> > > This serie is based on Yangtao Li serie[0] and Ondřej Jirman work[1].
> > >
> > > Most of the OPP tables are taken from original vendor kernel[2].
> > > Plus there is a new CPU frequencies at 1.6GHz, 1.7GHz and 1.8GHz.
> > >
> > > I wrote a simple script to randomly set a frequency during
> > > a random time[3].
> >
> > If you ever need to do that ever again, cpufreq-ljt-stress-test (found
> > here https://github.com/ssvb/cpuburn-arm) has proven to be very
> > reliable to detect cpufreq related issues. stress-ng might not be
> > enough since the (at least older) Allwinner SoCs tend to create cache
> > corruption when undervolted, and that might not be unnoticed by
> > stress-ng but will be catched by cpufreq-ljt-stress-test.

The test seems good (see result below) :

# cpufreq-ljt-stress-test
Creating './whitenoise-1920x1080.jpg' ... done
CPU stress test, which is doing JPEG decoding by libjpeg-turbo
at different cpufreq operating points.

Testing CPU 0
1800 MHz ............................................................ OK
1704 MHz ............................................................ OK
1608 MHz ............................................................ OK
1488 MHz ............................................................ OK
1320 MHz ............................................................ OK
1080 MHz ............................................................ OK
888 MHz ............................................................ OK
816 MHz ............................................................ OK
720 MHz ............................................................ OK
480 MHz ............................................................ OK

Testing CPU 1
1800 MHz ............................................................ OK
1704 MHz ............................................................ OK
1608 MHz ............................................................ OK
1488 MHz ............................................................ OK
1320 MHz ............................................................ OK
1080 MHz ............................................................ OK
888 MHz ............................................................ OK
816 MHz ............................................................ OK
720 MHz ............................................................ OK
480 MHz ............................................................ OK

Testing CPU 2
1800 MHz ............................................................ OK
1704 MHz ............................................................ OK
1608 MHz ............................................................ OK
1488 MHz ............................................................ OK
1320 MHz ............................................................ OK
1080 MHz ............................................................ OK
888 MHz ............................................................ OK
816 MHz ............................................................ OK
720 MHz ............................................................ OK
480 MHz ............................................................ OK

Testing CPU 3
1800 MHz ............................................................ OK
1704 MHz ............................................................ OK
1608 MHz ............................................................ OK
1488 MHz ............................................................ OK
1320 MHz ............................................................ OK
1080 MHz ............................................................ OK
888 MHz ............................................................ OK
816 MHz ............................................................ OK
720 MHz ............................................................ OK
480 MHz ............................................................ OK

Overall result : PASSED

[Clément Péron]

Hi Sunxi maintainers and members,

Now that required drivers are merged we can contibute on DVFS
support for Allwinner H6.

This serie is based on Yangtao Li serie[0] and Ondřej Jirman work[1].

Most of the OPP tables are taken from original vendor kernel[2].

Plus there are new CPU frequencies at 1.6GHz, 1.7GHz and 1.8GHz.

I wrote a simple script to randomly set a frequency during

a random time[3]. This script is quite stressfull and set some high
frequency without checking temperature. This can result on behavior
that whould not occurs with the real cpufreq framework.
As Maxime point out I also tested with cpufreq-ljt-stress-test
(found here https://github.com/ssvb/cpuburn-arm).
This script doesn't trigger any issue.

I also test that that offlining CPU0 and doing DVFS on other CPUs
works. As CPU regulator is only set for CPU0.

The GPU devfreq was drop as the regulator is still not properly
drive by panfrost driver[4].
I will re-introduce it later.

Ondřej Jirman has an Orange Pi 3, Jernej has a PineH64 and a Tanix
TX6 boards and I have a Beelink GS1 board so I have enable these
boards. But CPU Devfreq is really touchy has it depends on:
board design, SoC speed_grade and environement which can affect
thermal cooling and have different behavior for different user.

If people can test this serie and give feedback, I will try to
introduce this in LibreElec tree, so LE community can test it.

Thanks,
Clément

0: https://patchwork.kernel.org/cover/10815117/
1: https://megous.com/git/linux/log/?h=ths-5.7
2: https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi#L345-L517
3: https://gist.github.com/clementperon/55a055dae3f13bbd14fb39c0069fe2e2

4: https://patchwork.kernel.org/patch/11486893/

Changes since v2 (thanks to Maxime Ripard):
- Change Orange Pi boards to Orange Pi 3
- Change soc speed nvmem node name
- Fix device tree warnings
- Drop GPU opp tables

Changes since v1 (thanks to Ondřej Jirman):
- Remove Polling thermal
- Add Orange Pi boards
- Remove minimal voltage change for Beelink GS1
- Add ramp-deplay for GPU and CPU regulators
- Push to thermal point to 85°C (Allwinner set them to 100°C and 115°C)
- Added 1.6GHz and 1.7GHz to OPP table.

Clément Péron (6):

arm64: configs: Enable sun50i cpufreq nvmem

arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1
arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3
arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6
arm64: dts: allwinner: Sort Pine H64 device-tree nodes
arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Pine H64

Ondrej Jirman (1):

arm64: dts: allwinner: h6: Add CPU Operating Performance Points table

.../dts/allwinner/sun50i-h6-beelink-gs1.dts | 9 +-
.../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 121 ++++++++++++++++++
.../dts/allwinner/sun50i-h6-orangepi-3.dts | 3 +
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 41 +++---
.../dts/allwinner/sun50i-h6-tanix-tx6.dts | 13 ++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 +
arch/arm64/configs/defconfig | 1 +
7 files changed, 174 insertions(+), 18 deletions(-)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi

--
2.20.1

[Clément Péron]

Allwinner H6 needs this driver to be able to get
the correct speed_bin required for DVFS.

Enable this option in arm64 defconfig.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig

index f9eefb5940ca..37e512c135ba 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -84,6 +84,7 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
CONFIG_CPUFREQ_DT=y
CONFIG_ACPI_CPPC_CPUFREQ=m
+CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m

[Clément Péron]

Enable CPU opp tables for Beelink GS1.

This needs to change the CPU regulator max voltage to fit
the OPP table.

Also add the ramp-delay information to avoid any out of spec
running as the regulator is slower at reaching the voltage
requested compare to the PLL reaching the frequency.

There is no such information for AXP805 but similar PMIC (AXP813)
has a DVM (Dynamic Voltage scaling Management) ramp rate equal
to 2500uV/us.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 8f09d209359b..3f7ceeb1a767 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -4,6 +4,7 @@

/dts-v1/;

#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"

#include <dt-bindings/gpio/gpio.h>

@@ -77,6 +78,10 @@

};
};

+&cpu0 {
+ cpu-supply = <&reg_dcdca>;
+};
+

&de {
status = "okay";
};
@@ -234,7 +239,8 @@

reg_dcdca: dcdca {
regulator-always-on;
regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1080000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-ramp-delay = <2500>;
regulator-name = "vdd-cpu";
};

@@ -242,6 +248,7 @@

[Clément Péron]

Enable CPU opp tables for Orange Pi 3.

This needs to change the CPU regulator max voltage to fit
the OPP table.

Also add the ramp-delay information to avoid any out of spec
running as the regulator is slower at reaching the voltage
requested compare to the PLL reaching the frequency.

There is no such information for AXP805 but similar PMIC (AXP813)
has a DVM (Dynamic Voltage scaling Management) ramp rate equal
to 2500uV/us.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 3 +++
1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index 47f579610dcc..15c9dd8c4479 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts

@@ -4,6 +4,7 @@
/dts-v1/;

#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"

#include <dt-bindings/gpio/gpio.h>

@@ -257,6 +258,7 @@
regulator-always-on;
regulator-min-microvolt = <800000>;

regulator-max-microvolt = <1160000>;
+ regulator-ramp-delay = <2500>;
regulator-name = "vdd-cpu";
};

@@ -264,6 +266,7 @@

[Clément Péron]

Enable CPU opp tables for Tanix TX6.

Also add the fixed regulator that provided vdd-cpu-gpu required for
CPU opp tables.

This voltage has been found using a voltmeter and could be wrong.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

.../boot/dts/allwinner/sun50i-h6-tanix-tx6.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
index 83e6cb0e59ce..be81330db14f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts

@@ -4,6 +4,7 @@
/dts-v1/;

#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"

#include <dt-bindings/gpio/gpio.h>

@@ -37,6 +38,17 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ reg_vdd_cpu_gpu: vdd-cpu-gpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu-gpu";
+ regulator-min-microvolt = <1135000>;
+ regulator-max-microvolt = <1135000>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpu_gpu>;
};

&de {
@@ -56,6 +68,7 @@
};

&gpu {
+ mali-supply = <&reg_vdd_cpu_gpu>;
status = "okay";
};

--
2.20.1

[Clément Péron]

Pine H64 device-tree have some nodes not properly sorted.

Fix this.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 34 +++++++++----------
1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index b0642d841933..63a785b534e1 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -80,6 +80,18 @@
};
};

+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
&emac {
pinctrl-names = "default";
pinctrl-0 = <&ext_rgmii_pins>;
@@ -91,17 +103,6 @@
status = "okay";
};

-&mdio {
- ext_rgmii_phy: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
-};
-
-&de {
- status = "okay";
-};
-
&gpu {
mali-supply = <&reg_dcdcc>;
status = "okay";
@@ -117,12 +118,11 @@
};
};

-&ehci0 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
};

&mmc0 {
--
2.20.1

[Clément Péron]

Enable CPU and GPU opp tables for Pine H64.

Also add the ramp-delay information to avoid any out of spec
running as the regulator is slower at reaching the voltage
requested compare to the PLL reaching the frequency.

There is no such information for AXP805 but similar PMIC (AXP813)
has a DVM (Dynamic Voltage scaling Management) ramp rate equal
to 2500uV/us.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 63a785b534e1..60fd33f657dc 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts

@@ -4,6 +4,7 @@
/dts-v1/;

#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"

#include <dt-bindings/gpio/gpio.h>

@@ -80,6 +81,10 @@

};
};

+&cpu0 {
+ cpu-supply = <&reg_dcdca>;
+};
+
&de {
status = "okay";
};

@@ -239,6 +244,7 @@
regulator-always-on;

regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
+ regulator-ramp-delay = <2500>;

regulator-name = "vdd-cpu";
};

@@ -246,6 +252,7 @@

[Ondřej Jirman]

Hello Clément,

On Sun, Apr 19, 2020 at 03:50:04PM +0200, Clément Péron wrote:
> Hi Sunxi maintainers and members,
>
> Now that required drivers are merged we can contibute on DVFS
> support for Allwinner H6.
>

[ snip ]

>
> Changes since v2 (thanks to Maxime Ripard):
> - Change Orange Pi boards to Orange Pi 3
> - Change soc speed nvmem node name
> - Fix device tree warnings
> - Drop GPU opp tables

Looks like you may have also inadverently dropped the second patch from v2
series that implemented CPU thermal trip points.

> Changes since v1 (thanks to Ondřej Jirman):
> - Remove Polling thermal
> - Add Orange Pi boards
> - Remove minimal voltage change for Beelink GS1
> - Add ramp-deplay for GPU and CPU regulators
> - Push to thermal point to 85°C (Allwinner set them to 100°C and 115°C)
> - Added 1.6GHz and 1.7GHz to OPP table.
>
> Clément Péron (6):
> arm64: configs: Enable sun50i cpufreq nvmem
> arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1
> arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3
> arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6
> arm64: dts: allwinner: Sort Pine H64 device-tree nodes
> arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Pine H64

You may also want to fix title of this patch to drop the GPU reference.

thank you and regards,
o.

[Ondřej Jirman]

On Mon, Apr 20, 2020 at 11:48:01AM +0200, megous hlavni wrote:
> Hello Clément,
>
> On Sun, Apr 19, 2020 at 03:50:04PM +0200, Clément Péron wrote:
> > Hi Sunxi maintainers and members,
> >
> > Now that required drivers are merged we can contibute on DVFS
> > support for Allwinner H6.
> >
>
> [ snip ]
>
> >
> > Changes since v2 (thanks to Maxime Ripard):
> > - Change Orange Pi boards to Orange Pi 3
> > - Change soc speed nvmem node name
> > - Fix device tree warnings
> > - Drop GPU opp tables
>
> Looks like you may have also inadverently dropped the second patch from v2
> series that implemented CPU thermal trip points.

Also it looks like the patch 1 from v2 implementing the clock properties
is missing from v3, and I don't see it being already applied anywhere.
Without that cpufreq doesn't work.

Also, thermal trip points need to be in the opp.dtsi to avoid dtc warnings
during build.

https://megous.com/git/linux/commit/?h=ths-5.7&id=cacefd7decf5ae0ce42ab4d48a13a58552929ebd

regards,
o.

[Ondřej Jirman]

Hi Maxime,

On Mon, Apr 20, 2020 at 10:45:47AM +0200, Maxime Ripard wrote:
> Hi,

>
> On Sun, Apr 19, 2020 at 03:50:04PM +0200, Clément Péron wrote:

> Applied all of them, thanks!

Please also apply "[PATCH v2 1/7] arm64: dts: allwinner: h6: Add
clock to CPU cores" from the v2 series, otherwise cpufreq will
not work.

I can also send a missing patch adding the trip points, and cpu
as a cooling device, that I linked in my other reply to this patch
series afterwards, if Clément wants.

regards,
o.

> Maxime

[Clément Péron]

Hi Ondrej, Maxime,

Indeed I have sent using the following cmd : "git send-email --to=XXXX HEAD~7"
from the previous version.

I should had do Instead: "git send-email --to=XXXX next/master "

Sorry for that :(
Clément

>
> regards,
> o.
>
> > Maxime
>
>

[Clément Péron]

Hi Maxime,

I have sent the v3 serie with the same command as used for the v2.

$> git send-email --to=XXXX HEAD~7

Which is now wrong because I have introduced 2 new commits.

Sorry for that I should have used:

$> git send-email --to=XXXX next/master

Could you apply these patches before the other DVFS patches to keep
a clean order?

Thanks to Ondrej Jirman for the catch,
And sorry for the mistake,
Regards,
Clement

Ondrej Jirman (1):
arm64: dts: allwinner: h6: Add thermal trip points/cooling map

Yangtao Li (1):

arm64: dts: allwinner: h6: Add clock to CPU cores

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 32 ++++++++++++++++++++
1 file changed, 32 insertions(+)

--
2.20.1

[Clément Péron]

From: Yangtao Li <tiny....@gmail.com>

The ARM CPU cores are fed by the CPU clock from the CCU. Add a
reference to the clock for each CPU core, along with the clock
transition latency.

Signed-off-by: Yangtao Li <tiny....@gmail.com>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index a5ee68388bd3..370e77b86fe1 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi

@@ -25,6 +25,8 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;

+ clock-latency-ns = <244144>; /* 8 32k periods */

};

cpu1: cpu@1 {
@@ -32,6 +34,8 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;

+ clock-latency-ns = <244144>; /* 8 32k periods */

};

cpu2: cpu@2 {
@@ -39,6 +43,8 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;

+ clock-latency-ns = <244144>; /* 8 32k periods */

};

cpu3: cpu@3 {
@@ -46,6 +52,8 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;

+ clock-latency-ns = <244144>; /* 8 32k periods */

};
};

--
2.20.1

[Clément Péron]

From: Ondrej Jirman <meg...@megous.com>

This enables passive cooling by down-regulating CPU voltage
and frequency.

Signed-off-by: Ondrej Jirman <meg...@megous.com>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 24 ++++++++++++++++++++
1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 370e77b86fe1..60da1627772b 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -964,6 +964,30 @@

polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 0>;
+
+ trips {

+ cpu_alert: cpu-alert {

+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+

+ cpu-crit {

+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {

+ map0 {
+ trip = <&cpu_alert>;

[Clément Péron]

Hi Maxime

On Mon, 20 Apr 2020 at 14:47, Maxime Ripard <max...@cerno.tech> wrote:

> I haven't pushed anything yet, can you resend the proper branch?

Yes, I will,

Thanks!
>
> Thanks!
> Maxime

[Clément Péron]

Hi,

This is the same as v4 and v3 on top.
I have also fix the commit title for Pine H64 as we now only enable CPU DVFS.

Sorry for the noise,
Clément

Clément Péron (6):
arm64: configs: Enable sun50i cpufreq nvmem
arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1
arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3
arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6
arm64: dts: allwinner: Sort Pine H64 device-tree nodes

arm64: dts: allwinner: h6: Enable CPU opp tables for Pine H64

Ondrej Jirman (2):
arm64: dts: allwinner: h6: Add thermal trip points/cooling map

arm64: dts: allwinner: h6: Add CPU Operating Performance Points table

Yangtao Li (1):

arm64: dts: allwinner: h6: Add clock to CPU cores

.../dts/allwinner/sun50i-h6-beelink-gs1.dts | 9 +-
.../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 121 ++++++++++++++++++
.../dts/allwinner/sun50i-h6-orangepi-3.dts | 3 +

.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 43 ++++---
.../dts/allwinner/sun50i-h6-tanix-tx6.dts | 13 ++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 36 ++++++
arch/arm64/configs/defconfig | 1 +
7 files changed, 207 insertions(+), 19 deletions(-)

[Clément Péron]

From: Yangtao Li <tiny....@gmail.com>

The ARM CPU cores are fed by the CPU clock from the CCU. Add a
reference to the clock for each CPU core, along with the clock
transition latency.

Signed-off-by: Yangtao Li <tiny....@gmail.com>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index a5ee68388bd3..370e77b86fe1 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi

[Clément Péron]

From: Ondrej Jirman <meg...@megous.com>

Add an Operating Performance Points table for the CPU cores to
enable Dynamic Voltage & Frequency Scaling on the H6.

Signed-off-by: Ondrej Jirman <meg...@megous.com>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

.../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 121 ++++++++++++++++++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 +
2 files changed, 125 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
new file mode 100644

index 000000000000..9ebd97b04b1a

--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Ondrej Jirman <meg...@megous.com>
+// Copyright (C) 2020 Clément Péron <peron...@gmail.com>
+
+/ {

+ cpu_opp_table: cpu-opp-table {
+ compatible = "allwinner,sun50i-h6-operating-points";
+ nvmem-cells = <&cpu_speed_grade>;

+ opp-shared;
+
+ opp@480000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <480000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };

+
+ opp@720000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <720000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@816000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <816000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@888000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <888000000>;
+
+ opp-microvolt-speed0 = <880000>;
+ opp-microvolt-speed1 = <820000>;
+ opp-microvolt-speed2 = <820000>;
+ };
+
+ opp@1080000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <1080000000>;
+
+ opp-microvolt-speed0 = <940000>;
+ opp-microvolt-speed1 = <880000>;
+ opp-microvolt-speed2 = <880000>;
+ };
+
+ opp@1320000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <1320000000>;
+
+ opp-microvolt-speed0 = <1000000>;
+ opp-microvolt-speed1 = <940000>;
+ opp-microvolt-speed2 = <940000>;
+ };
+
+ opp@1488000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <1488000000>;
+
+ opp-microvolt-speed0 = <1060000>;
+ opp-microvolt-speed1 = <1000000>;
+ opp-microvolt-speed2 = <1000000>;
+ };
+
+ opp@1608000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <1608000000>;
+
+ opp-microvolt-speed0 = <1090000>;
+ opp-microvolt-speed1 = <1030000>;
+ opp-microvolt-speed2 = <1030000>;
+ };
+
+ opp@1704000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <1704000000>;
+
+ opp-microvolt-speed0 = <1120000>;
+ opp-microvolt-speed1 = <1060000>;
+ opp-microvolt-speed2 = <1060000>;
+ };
+
+ opp@1800000000 {

+ clock-latency-ns = <244144>; /* 8 32k periods */

+ opp-hz = /bits/ 64 <1800000000>;
+
+ opp-microvolt-speed0 = <1160000>;
+ opp-microvolt-speed1 = <1100000>;
+ opp-microvolt-speed2 = <1100000>;
+ };

+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;

+ #cooling-cells = <2>;
+};
+
+&cpu1 {

+ operating-points-v2 = <&cpu_opp_table>;

+ #cooling-cells = <2>;
+};
+
+&cpu2 {

+ operating-points-v2 = <&cpu_opp_table>;

+ #cooling-cells = <2>;
+};
+
+&cpu3 {

+ operating-points-v2 = <&cpu_opp_table>;

+ #cooling-cells = <2>;
+};

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 60da1627772b..83e32f9c4977 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -258,6 +258,10 @@
ths_calibration: thermal-sensor-calibration@14 {
reg = <0x14 0x8>;
};
+
+ cpu_speed_grade: cpu-speed-grade@1c {

+ reg = <0x1c 0x4>;
+ };

};

watchdog: watchdog@30090a0 {
--
2.20.1

[Clément Péron]

From: Ondrej Jirman <meg...@megous.com>

This enables passive cooling by down-regulating CPU voltage
and frequency.

Signed-off-by: Ondrej Jirman <meg...@megous.com>
Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 24 ++++++++++++++++++++
1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 370e77b86fe1..60da1627772b 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi

[Clément Péron]

Allwinner H6 needs this driver to be able to get
the correct speed_bin required for DVFS.

Enable this option in arm64 defconfig.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

[Clément Péron]

Enable CPU opp tables for Beelink GS1.

This needs to change the CPU regulator max voltage to fit
the OPP table.

Also add the ramp-delay information to avoid any out of spec
running as the regulator is slower at reaching the voltage
requested compare to the PLL reaching the frequency.

There is no such information for AXP805 but similar PMIC (AXP813)
has a DVM (Dynamic Voltage scaling Management) ramp rate equal
to 2500uV/us.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 8f09d209359b..3f7ceeb1a767 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts

@@ -4,6 +4,7 @@
/dts-v1/;

#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"

#include <dt-bindings/gpio/gpio.h>

@@ -77,6 +78,10 @@

};
};

+&cpu0 {
+ cpu-supply = <&reg_dcdca>;
+};
+
&de {
status = "okay";
};

@@ -234,7 +239,8 @@
reg_dcdca: dcdca {
regulator-always-on;
regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1080000>;
+ regulator-max-microvolt = <1160000>;

+ regulator-ramp-delay = <2500>;
regulator-name = "vdd-cpu";
};

@@ -242,6 +248,7 @@

[Clément Péron]

Enable CPU opp tables for Orange Pi 3.

This needs to change the CPU regulator max voltage to fit
the OPP table.

Also add the ramp-delay information to avoid any out of spec
running as the regulator is slower at reaching the voltage
requested compare to the PLL reaching the frequency.

There is no such information for AXP805 but similar PMIC (AXP813)
has a DVM (Dynamic Voltage scaling Management) ramp rate equal
to 2500uV/us.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 3 +++
1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index 47f579610dcc..15c9dd8c4479 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts

@@ -4,6 +4,7 @@
/dts-v1/;

#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"

#include <dt-bindings/gpio/gpio.h>

@@ -257,6 +258,7 @@
regulator-always-on;
regulator-min-microvolt = <800000>;

regulator-max-microvolt = <1160000>;
+ regulator-ramp-delay = <2500>;
regulator-name = "vdd-cpu";
};

@@ -264,6 +266,7 @@

[Clément Péron]

Enable CPU opp tables for Tanix TX6.

Also add the fixed regulator that provided vdd-cpu-gpu required for
CPU opp tables.

This voltage has been found using a voltmeter and could be wrong.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

.../boot/dts/allwinner/sun50i-h6-tanix-tx6.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
index 83e6cb0e59ce..be81330db14f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts

@@ -4,6 +4,7 @@
/dts-v1/;

#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"

#include <dt-bindings/gpio/gpio.h>

@@ -37,6 +38,17 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ reg_vdd_cpu_gpu: vdd-cpu-gpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu-gpu";
+ regulator-min-microvolt = <1135000>;
+ regulator-max-microvolt = <1135000>;

+ };
+};
+
+&cpu0 {

[Clément Péron]

Pine H64 device-tree have some nodes not properly sorted.

Fix this.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 34 +++++++++----------
1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index b0642d841933..63a785b534e1 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts

[Clément Péron]

Enable CPU and GPU opp tables for Pine H64.

This needs to change the CPU regulator max voltage to fit
the OPP table.

Also add the ramp-delay information to avoid any out of spec
running as the regulator is slower at reaching the voltage
requested compare to the PLL reaching the frequency.

There is no such information for AXP805 but similar PMIC (AXP813)
has a DVM (Dynamic Voltage scaling Management) ramp rate equal
to 2500uV/us.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 9 ++++++++-

1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 63a785b534e1..af85b2074867 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts

@@ -4,6 +4,7 @@
/dts-v1/;

#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"

#include <dt-bindings/gpio/gpio.h>

@@ -80,6 +81,10 @@

};
};

+&cpu0 {
+ cpu-supply = <&reg_dcdca>;
+};
+
&de {
status = "okay";
};

@@ -238,7 +243,8 @@

reg_dcdca: dcdca {
regulator-always-on;
regulator-min-microvolt = <810000>;
- regulator-max-microvolt = <1080000>;

+ regulator-max-microvolt = <1160000>;

+ regulator-ramp-delay = <2500>;
regulator-name = "vdd-cpu";
};

@@ -246,6 +252,7 @@

[Ondřej Jirman]

Hi,

On Mon, Apr 20, 2020 at 03:00:14PM +0200, Clément Péron wrote:
> From: Ondrej Jirman <meg...@megous.com>
>
> This enables passive cooling by down-regulating CPU voltage
> and frequency.

Does this not produce a lot of warnings for you during compilation?

regards,
o.

[Clément Péron]

Hi Ondrej,

On Mon, 20 Apr 2020 at 15:46, Ondřej Jirman <meg...@megous.com> wrote:
>
> Hi,
>
> On Mon, Apr 20, 2020 at 03:00:14PM +0200, Clément Péron wrote:
> > From: Ondrej Jirman <meg...@megous.com>
> >
> > This enables passive cooling by down-regulating CPU voltage
> > and frequency.
>
> Does this not produce a lot of warnings for you during compilation?

I got flooded by lots of warnings, from sun50i-a64, stringray-usb,
ipq6018 and didn't see but two are from sun50i-h6.

The #cooling-cells property is missing for CPU.

Will send a patch for noticing.

Regard,
Clement