[PATCH v3 0/8] Allwinner H6 Mali GPU support

[Clément Péron]

Hi,

The Allwinner H6 has a Mali-T720 MP2. The drivers are
out-of-tree so this series only introduce the dt-bindings.

The first patch is from Neil Amstrong and has been already
merged in linux-amlogic. It is required for this series.

The second patch is from Icenowy Zheng where I changed the
order has required by Rob Herring.
See: https://patchwork.kernel.org/patch/10699829/

Thanks,
Clement

Changes in v3 (Thanks to Maxime Ripard):
- Reauthor Icenowy for her path

Changes in v2 (Thanks to Maxime Ripard):
- Drop GPU OPP Table
- Add clocks and clock-names in required

Clément Péron (6):
dt-bindings: gpu: mali-midgard: Add h6 mali gpu compatible
arm64: dts: allwinner: Add ARM Mali GPU node for H6
arm64: dts: allwinner: Add mali GPU supply for Pine H64
arm64: dts: allwinner: Add mali GPU supply for Beelink GS1
arm64: dts: allwinner: Add mali GPU supply for OrangePi Boards
arm64: dts: allwinner: Add mali GPU supply for OrangePi 3

Icenowy Zheng (1):
dt-bindings: gpu: mali-midgard: Add bus clock bindings

Neil Armstrong (1):
dt-bindings: gpu: mali-midgard: Add resets property

.../bindings/gpu/arm,mali-midgard.txt | 27 +++++++++++++++++++
.../dts/allwinner/sun50i-h6-beelink-gs1.dts | 5 ++++
.../dts/allwinner/sun50i-h6-orangepi-3.dts | 5 ++++
.../dts/allwinner/sun50i-h6-orangepi.dtsi | 5 ++++
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 5 ++++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++++++++++
6 files changed, 61 insertions(+)

--
2.17.1

[Clément Péron]

From: Neil Armstrong <narms...@baylibre.com>

The Amlogic ARM Mali Midgard requires reset controls to power on and
software reset the GPU, adds these as optional in the bindings.

Signed-off-by: Neil Armstrong <narms...@baylibre.com>
Reviewed-by: Rob Herring <ro...@kernel.org>
Signed-off-by: Kevin Hilman <khi...@baylibre.com>
---
.../devicetree/bindings/gpu/arm,mali-midgard.txt | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
index 18a2cde2e5f3..1b1a74129141 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
@@ -37,6 +37,20 @@ Optional properties:
- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
for details.

+- resets : Phandle of the GPU reset line.
+
+Vendor-specific bindings
+------------------------
+
+The Mali GPU is integrated very differently from one SoC to
+another. In order to accomodate those differences, you have the option
+to specify one more vendor-specific compatible, among:
+
+- "amlogic,meson-gxm-mali"
+ Required properties:
+ - resets : Should contain phandles of :
+ + GPU reset line
+ + GPU APB glue reset line

Example for a Mali-T760:

--
2.17.1

[Clément Péron]

From: Icenowy Zheng <ice...@aosc.io>

Some SoCs adds a bus clock gate to the Mali Midgard GPU.

Add the binding for the bus clock.

Signed-off-by: Icenowy Zheng <ice...@aosc.io>
Signed-off-by: Clément Péron <peron...@gmail.com>
---
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
index 1b1a74129141..2e8bbce35695 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
@@ -31,6 +31,12 @@ Optional properties:

- clocks : Phandle to clock for the Mali Midgard device.

+- clock-names : Specify the names of the clocks specified in clocks
+ when multiple clocks are present.
+ * core: clock driving the GPU itself (When only one clock is present,
+ assume it's this clock.)
+ * bus: bus clock for the GPU
+
- mali-supply : Phandle to regulator for the Mali device. Refer to
Documentation/devicetree/bindings/regulator/regulator.txt for details.

--
2.17.1

[Clément Péron]

This add the H6 mali compatible in the dt-bindings to later support
specific implementation.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

.../devicetree/bindings/gpu/arm,mali-midgard.txt | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
index 2e8bbce35695..4bf17e1cf555 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
@@ -15,6 +15,7 @@ Required properties:
+ "arm,mali-t860"
+ "arm,mali-t880"
* which must be preceded by one of the following vendor specifics:
+ + "allwinner,sun50i-h6-mali"
+ "amlogic,meson-gxm-mali"
+ "rockchip,rk3288-mali"
+ "rockchip,rk3399-mali"
@@ -49,9 +50,15 @@ Vendor-specific bindings
------------------------

The Mali GPU is integrated very differently from one SoC to

-another. In order to accomodate those differences, you have the option
+another. In order to accommodate those differences, you have the option

to specify one more vendor-specific compatible, among:

+- "allwinner,sun50i-h6-mali"
+ Required properties:
+ - clocks : phandles to core and bus clocks
+ - clock-names : must contain "core" and "bus"
+ - resets: phandle to GPU reset line
+
- "amlogic,meson-gxm-mali"
Required properties:

- resets : Should contain phandles of :

--
2.17.1

[Clément Péron]

Add the mali gpu node to the H6 device-tree.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++++++++++++++

1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 16c5c3d0fd81..6aad06095c40 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -157,6 +157,20 @@
allwinner,sram = <&ve_sram 1>;
};

+ gpu: gpu@1800000 {
+ compatible = "allwinner,sun50i-h6-mali",
+ "arm,mali-t720";
+ reg = <0x01800000 0x4000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "job", "mmu", "gpu";
+ clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
+ clock-names = "core", "bus";
+ resets = <&ccu RST_BUS_GPU>;
+ status = "disabled";
+ };
+
syscon: syscon@3000000 {
compatible = "allwinner,sun50i-h6-system-control",
"allwinner,sun50i-a64-system-control";
--
2.17.1

[Clément Péron]

Enable and add supply to the Mali GPU node on the
Pine H64 board.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 4802902e128f..e16a8c6738f9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -85,6 +85,11 @@
status = "okay";
};

+&gpu {
+ mali-supply = <&reg_dcdcc>;
+ status = "okay";
+};
+
&hdmi {
status = "okay";
};
--
2.17.1

[Clément Péron]

Enable and add supply to the Mali GPU node on the

Beelink GS1 board.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 5 +++++

1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 0dc33c90dd60..21440d572f0a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -70,6 +70,11 @@

[Clément Péron]

Enable and add supply to the Mali GPU node on the

Orange Pi One Plus and Lite2 boards.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 5 +++++

1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
index 62e27948a3fa..bd13297555ab 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
@@ -55,6 +55,11 @@

status = "okay";
};

+&gpu {
+ mali-supply = <&reg_dcdcc>;
+ status = "okay";
+};
+

&mmc0 {
vmmc-supply = <&reg_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
--
2.17.1

[Clément Péron]

Enable and add supply to the Mali GPU node on the

Orange Pi 3 board.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 5 +++++

1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index 17d496990108..d4c989cc92a7 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -58,6 +58,11 @@

status = "okay";
};

+&gpu {
+ mali-supply = <&reg_dcdcc>;
+ status = "okay";
+};
+
&mmc0 {
vmmc-supply = <&reg_cldo1>;

cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
--
2.17.1

[Rob Herring]

On Wed, Apr 17, 2019 at 07:30:25PM +0200, Clément Péron wrote:
> From: Icenowy Zheng <ice...@aosc.io>
>
> Some SoCs adds a bus clock gate to the Mali Midgard GPU.
>
> Add the binding for the bus clock.
>
> Signed-off-by: Icenowy Zheng <ice...@aosc.io>
> Signed-off-by: Clément Péron <peron...@gmail.com>
> ---
> Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++++++
> 1 file changed, 6 insertions(+)

The panfrost driver is merged now (to drm-misc) if you want to add
support for the 2nd clock.

Reviewed-by: Rob Herring <ro...@kernel.org>

[Rob Herring]

On Wed, 17 Apr 2019 19:30:26 +0200, =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= wrote:
> This add the H6 mali compatible in the dt-bindings to later support
> specific implementation.
>
> Signed-off-by: Clément Péron <peron...@gmail.com>
> ---
> .../devicetree/bindings/gpu/arm,mali-midgard.txt | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>

Reviewed-by: Rob Herring <ro...@kernel.org>

[Clément Péron]

Hi Maxime,

Is this series ok for you ?

Thanks,
Clement

[Maxime Ripard]

On Sat, May 11, 2019 at 06:39:39PM +0200, Clément Péron wrote:
> Hi Maxime,
>
> Is this series ok for you ?

I'm not the maintainer of that binding, so I'd need a ack from whoever
that is.

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[Clément Péron]

Hi,

On Sun, 12 May 2019 at 15:45, Maxime Ripard <maxime...@bootlin.com> wrote:
>
> On Sat, May 11, 2019 at 06:39:39PM +0200, Clément Péron wrote:
> > Hi Maxime,
> >
> > Is this series ok for you ?
>
> I'm not the maintainer of that binding, so I'd need a ack from whoever
> that is.

Indeed, I will collect Rob H. reviewed and resent with the correct maintainer.

Regards,
Clement

[peron...@gmail.com]

From: Clément Péron <peron...@gmail.com>

Hi,

The Allwinner H6 has a Mali-T720 MP2. The drivers are
out-of-tree so this series only introduce the dt-bindings.

The first patch is from Neil Amstrong and has been already
merged in linux-amlogic. It is required for this series.

The second patch is from Icenowy Zheng where I changed the
order has required by Rob Herring.
See: https://patchwork.kernel.org/patch/10699829/

Thanks,

Clément

Changes in v4:
- Add Rob Herring reviewed-by tag
- Resent with correct Maintainers

Changes in v3 (Thanks to Maxime Ripard):

- Reauthor Icenowy for her patch

Changes in v2 (Thanks to Maxime Ripard):
- Drop GPU OPP Table
- Add clocks and clock-names in required

Clément Péron (6):

dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible

arm64: dts: allwinner: Add ARM Mali GPU node for H6
arm64: dts: allwinner: Add mali GPU supply for Pine H64
arm64: dts: allwinner: Add mali GPU supply for Beelink GS1
arm64: dts: allwinner: Add mali GPU supply for OrangePi Boards
arm64: dts: allwinner: Add mali GPU supply for OrangePi 3

Icenowy Zheng (1):

dt-bindings: gpu: add bus clock for Mali Midgard GPUs

[peron...@gmail.com]

From: Neil Armstrong <narms...@baylibre.com>

The Amlogic ARM Mali Midgard requires reset controls to power on and
software reset the GPU, adds these as optional in the bindings.

Signed-off-by: Neil Armstrong <narms...@baylibre.com>
Reviewed-by: Rob Herring <ro...@kernel.org>
Signed-off-by: Kevin Hilman <khi...@baylibre.com>
---

.../devicetree/bindings/gpu/arm,mali-midgard.txt | 14 ++++++++++++++

1 file changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
index 18a2cde2e5f3..1b1a74129141 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt

@@ -37,6 +37,20 @@ Optional properties:
- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
for details.

+- resets : Phandle of the GPU reset line.
+
+Vendor-specific bindings
+------------------------
+

+The Mali GPU is integrated very differently from one SoC to
+another. In order to accomodate those differences, you have the option
+to specify one more vendor-specific compatible, among:
+
+- "amlogic,meson-gxm-mali"
+ Required properties:

[peron...@gmail.com]

From: Icenowy Zheng <ice...@aosc.io>

Some SoCs adds a bus clock gate to the Mali Midgard GPU.

Add the binding for the bus clock.

Signed-off-by: Icenowy Zheng <ice...@aosc.io>
Signed-off-by: Clément Péron <peron...@gmail.com>

Reviewed-by: Rob Herring <ro...@kernel.org>
---
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
index 1b1a74129141..2e8bbce35695 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt

[peron...@gmail.com]

From: Clément Péron <peron...@gmail.com>

This add the H6 mali compatible in the dt-bindings to later support
specific implementation.

Signed-off-by: Clément Péron <peron...@gmail.com>
Reviewed-by: Rob Herring <ro...@kernel.org>
---

.../devicetree/bindings/gpu/arm,mali-midgard.txt | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
index 2e8bbce35695..4bf17e1cf555 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt

@@ -15,6 +15,7 @@ Required properties:
+ "arm,mali-t860"
+ "arm,mali-t880"
* which must be preceded by one of the following vendor specifics:
+ + "allwinner,sun50i-h6-mali"
+ "amlogic,meson-gxm-mali"
+ "rockchip,rk3288-mali"
+ "rockchip,rk3399-mali"
@@ -49,9 +50,15 @@ Vendor-specific bindings
------------------------

The Mali GPU is integrated very differently from one SoC to

-another. In order to accomodate those differences, you have the option

+another. In order to accommodate those differences, you have the option

to specify one more vendor-specific compatible, among:

+- "allwinner,sun50i-h6-mali"
+ Required properties:

+ - clocks : phandles to core and bus clocks
+ - clock-names : must contain "core" and "bus"
+ - resets: phandle to GPU reset line
+
- "amlogic,meson-gxm-mali"
Required properties:

- resets : Should contain phandles of :

--
2.17.1

[peron...@gmail.com]

From: Clément Péron <peron...@gmail.com>

Add the mali gpu node to the H6 device-tree.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++++++++++++++

1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index e0dc4a05c1ba..196753110434 100644

[peron...@gmail.com]

From: Clément Péron <peron...@gmail.com>

Enable and add supply to the Mali GPU node on the

Pine H64 board.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 5 +++++

1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 4802902e128f..e16a8c6738f9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts

@@ -85,6 +85,11 @@

status = "okay";
};

+&gpu {
+ mali-supply = <&reg_dcdcc>;
+ status = "okay";
+};
+

[peron...@gmail.com]

From: Clément Péron <peron...@gmail.com>

Enable and add supply to the Mali GPU node on the

Beelink GS1 board.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 5 +++++

1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 0dc33c90dd60..21440d572f0a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts

@@ -70,6 +70,11 @@

[peron...@gmail.com]

From: Clément Péron <peron...@gmail.com>

Enable and add supply to the Mali GPU node on the

Orange Pi One Plus and Lite2 boards.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 5 +++++

1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
index 62e27948a3fa..bd13297555ab 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi

@@ -55,6 +55,11 @@

status = "okay";
};

+&gpu {
+ mali-supply = <&reg_dcdcc>;
+ status = "okay";
+};
+

&mmc0 {
vmmc-supply = <&reg_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;

--
2.17.1

[peron...@gmail.com]

From: Clément Péron <peron...@gmail.com>

Enable and add supply to the Mali GPU node on the

Orange Pi 3 board.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 5 +++++

1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index 17d496990108..d4c989cc92a7 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts

@@ -58,6 +58,11 @@

status = "okay";
};

+&gpu {
+ mali-supply = <&reg_dcdcc>;
+ status = "okay";
+};
+
&mmc0 {
vmmc-supply = <&reg_cldo1>;

[Jagan Teki]

I think we can squash all these board dts changes into single patch.

[Daniel Vetter]

On Sun, May 12, 2019 at 07:46:00PM +0200, peron...@gmail.com wrote:
> From: Clément Péron <peron...@gmail.com>
>
> Hi,
>
> The Allwinner H6 has a Mali-T720 MP2. The drivers are
> out-of-tree so this series only introduce the dt-bindings.

We do have an in-tree midgard driver now (since 5.2). Does this stuff work
together with your dt changes here?
-Daniel

--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

[Chen-Yu Tsai]

Yes. Please do so for all patches with the same changes applied to different
boards, and authored by the same person.

ChenYu

[Clément Péron]

Hi,

On Tue, 14 May 2019 at 12:29, Neil Armstrong <narms...@baylibre.com> wrote:
>
> Hi,

>
> On 13/05/2019 17:14, Daniel Vetter wrote:
> > On Sun, May 12, 2019 at 07:46:00PM +0200, peron...@gmail.com wrote:
> >> From: Clément Péron <peron...@gmail.com>
> >>
> >> Hi,
> >>
> >> The Allwinner H6 has a Mali-T720 MP2. The drivers are
> >> out-of-tree so this series only introduce the dt-bindings.
> >
> > We do have an in-tree midgard driver now (since 5.2). Does this stuff work
> > together with your dt changes here?
>

> No, but it should be easy to add.
I will give it a try and let you know.

>
> Clément, no need to resend the first patch, it's now on
> linus master.
Ok

Thanks,
Clement

>
> Could you also add support for the bus clock in panfrost
> in the same patchset since it's also on master now ?
>
> Neil

[Clément Péron]

Hi Jagan, Chen-Yu,

I thought it was required to have "smallest" patch as possible.
And it's also better for tracking "Tested-by" tag.

I will squash them in the next version.

Thanks,
Clement
>
> ChenYu

[Clément Péron]

Hi,

On Tue, 14 May 2019 at 17:17, Clément Péron <peron...@gmail.com> wrote:
>
> Hi,
>
> On Tue, 14 May 2019 at 12:29, Neil Armstrong <narms...@baylibre.com> wrote:
> >
> > Hi,
> >
> > On 13/05/2019 17:14, Daniel Vetter wrote:
> > > On Sun, May 12, 2019 at 07:46:00PM +0200, peron...@gmail.com wrote:
> > >> From: Clément Péron <peron...@gmail.com>
> > >>
> > >> Hi,
> > >>
> > >> The Allwinner H6 has a Mali-T720 MP2. The drivers are
> > >> out-of-tree so this series only introduce the dt-bindings.
> > >
> > > We do have an in-tree midgard driver now (since 5.2). Does this stuff work
> > > together with your dt changes here?
> >
> > No, but it should be easy to add.
> I will give it a try and let you know.

Added the bus_clock and a ramp delay to the gpu_vdd but the driver
fail at probe.

[ 3.052919] panfrost 1800000.gpu: clock rate = 432000000
[ 3.058278] panfrost 1800000.gpu: bus_clock rate = 100000000
[ 3.179772] panfrost 1800000.gpu: mali-t720 id 0x720 major 0x1
minor 0x1 status 0x0
[ 3.187432] panfrost 1800000.gpu: features: 00000000,10309e40,
issues: 00000000,21054400
[ 3.195531] panfrost 1800000.gpu: Features: L2:0x07110206
Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002821 AS:0xf
JS:0x7
[ 3.207178] panfrost 1800000.gpu: shader_present=0x3 l2_present=0x1
[ 3.238257] panfrost 1800000.gpu: Fatal error during GPU init
[ 3.244165] panfrost: probe of 1800000.gpu failed with error -12

The ENOMEM is coming from "panfrost_mmu_init"
alloc_io_pgtable_ops(ARM_MALI_LPAE, &pfdev->mmu->pgtbl_cfg,
pfdev);

Which is due to a check in the pgtable alloc "cfg->ias != 48"
arm-lpae io-pgtable: arm_mali_lpae_alloc_pgtable cfg->ias 33 cfg->oas 40

DRI stack is totally new for me, could you give me a little clue about
this issue ?

Thanks,
Clément

[Robin Murphy]

Heh, this is probably the one bit which doesn't really count as "DRI stack".

That's merely a somewhat-conservative sanity check - I'm pretty sure it
*should* be fine to change the test to "cfg->ias > 48" (io-pgtable
itself ought to cope). You'll just get to be the first to actually test
a non-48-bit configuration here :)

Robin.

[Clément Péron]

Hi Robin,

Thanks a lot, the probe seems fine now :)

I try to run glmark2 :
# glmark2-es2-drm
=======================================================
glmark2 2017.07
=======================================================
OpenGL Information
GL_VENDOR: panfrost
GL_RENDERER: panfrost
GL_VERSION: OpenGL ES 2.0 Mesa 19.1.0-rc2
=======================================================
[build] use-vbo=false:

But it seems that H6 is not so easy to add :(.

[ 345.204813] panfrost 1800000.gpu: mmu irq status=1
[ 345.209617] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
0x0000000002400400
[ 345.209617] Reason: TODO
[ 345.209617] raw fault status: 0x800002C1
[ 345.209617] decoded fault status: SLAVE FAULT
[ 345.209617] exception type 0xC1: TRANSLATION_FAULT_LEVEL1
[ 345.209617] access type 0x2: READ
[ 345.209617] source id 0x8000
[ 345.729957] panfrost 1800000.gpu: gpu sched timeout, js=0,
status=0x8, head=0x2400400, tail=0x2400400, sched_job=000000009e204de9
[ 346.055876] panfrost 1800000.gpu: mmu irq status=1
[ 346.060680] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
0x0000000002C00A00
[ 346.060680] Reason: TODO
[ 346.060680] raw fault status: 0x810002C1
[ 346.060680] decoded fault status: SLAVE FAULT
[ 346.060680] exception type 0xC1: TRANSLATION_FAULT_LEVEL1
[ 346.060680] access type 0x2: READ
[ 346.060680] source id 0x8100
[ 346.561955] panfrost 1800000.gpu: gpu sched timeout, js=1,
status=0x8, head=0x2c00a00, tail=0x2c00a00, sched_job=00000000b55a9a85
[ 346.573913] panfrost 1800000.gpu: mmu irq status=1
[ 346.578707] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
0x0000000002C00B80
[ 346.578707] Reason: TODO
[ 346.578707] raw fault status: 0x800002C1
[ 346.578707] decoded fault status: SLAVE FAULT
[ 346.578707] exception type 0xC1: TRANSLATION_FAULT_LEVEL1
[ 346.578707] access type 0x2: READ
[ 346.578707] source id 0x8000
[ 347.073947] panfrost 1800000.gpu: gpu sched timeout, js=0,
status=0x8, head=0x2c00b80, tail=0x2c00b80, sched_job=00000000cf6af8e8
[ 347.104125] panfrost 1800000.gpu: mmu irq status=1
[ 347.108930] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
0x0000000002800900
[ 347.108930] Reason: TODO
[ 347.108930] raw fault status: 0x810002C1
[ 347.108930] decoded faultn thi status: SLAVE FAULT
[ 347.108930] exception type 0xC1: TRANSLATION_FAULT_LEVEL1
[ 347.108930] access type 0x2: READ
[ 347.108930] source id 0x8100
[ 347.617950] panfrost 1800000.gpu: gpu sched timeout, js=1,
status=0x8, head=0x2800900, tail=0x2800900, sched_job=000000009325fdb7
[ 347.629902] panfrost 1800000.gpu: mmu irq status=1
[ 347.634696] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
0x0000000002800A80

Regards,
Clement

>
> Robin.

[Robin Murphy]

On 16/05/2019 00:22, Rob Herring wrote:

> Is this 32 or 64 bit userspace? I think 64-bit does not work with
> T7xx. You might need this[1].

[ Oooh... that makes T620 actually do stuff without falling over
dereferencing VA 0 somewhere halfway through the job chain :D

I shall continue to play... ]

> You may also be the first to try T720,
> so it could be something else.

I was expecting to see a similar behaviour to my T620 (which I now
assume was down to 64-bit job descriptors sort-of-but-not-quite working)
but this does look a bit more fundamental - the fact that it's a level 1
fault with VA == head == tail suggests to me that the MMU can't see the
page tables at all to translate anything. I really hope that the H6 GPU
integration doesn't suffer from the same DMA offset as the Allwinner
display pipeline stuff, because that would be a real pain to support in
io-pgtable.

Robin.

[Jernej Škrabec]

Hi!

Dne četrtek, 16. maj 2019 ob 13:19:06 CEST je Robin Murphy napisal(a):

DMA offset is present only on early SoCs with DE1. DE2 and DE3 (used on H6)
have no offset.

Best regards,
Jernej