Hi!
"Not exactly.
...
to be able fo fix it that far."
It looks like your SPL is built with wrong MTD driver settings. SPL itself is
read by BROM, but U-Boot Proper is read by SPL. So MTD/NAND part of SPL has to
be configured correctly. I think first you should figure out what NAND chip
you use - you didn't mention which one. Mine is Micron, it was supported out
of the box. Get params of your NAND from datasheet then configure SPL to make
it use correct parameters, rebuild and go.
I'm not PRO in MTD/NAND devices but as I remember, NAND doesn't contain all
params of itself, so you need to specify them. You mentioned "adding NAND id" -
maybe in your case you'll have to do this (drivers/mtd/nand/nand_ids.c).
You've mentioned DT. SPL includes reduced part of DT. I didn't modify DT of
U-Boot at all. SPL is loaded by BROM, it loads U-Boot Proper in RAM with it's
hardcoded params ("SPL" in CONFIG_NAND_SUNXI_SPL_XXX config lines also points to
that these params are not loaded from DT by SPL), then (in my case) Proper reads
DT for kernel from SATA, loads kernel and boots it.
If your SPL is flashed correctly (if it starts - it is flashed correctly) then
you can get some hints about your NAND while flashing - FEX outputs some info
about it. In my case it is (with some my comments):
[SCAN_DBG] ==============Nand Architecture Parameter==============
[SCAN_DBG] Nand Chip ID: 0x4b44642c 0xffffffa9
[SCAN_DBG] Nand Chip Count: 0x1
[SCAN_DBG] Nand Chip Connect: 0x1
[SCAN_DBG] Nand Rb Connect Mode: 0x1
[SCAN_DBG] Sector Count Of Page: 0x10 // 16
[SCAN_DBG] Page Count Of Block: 0x100 // 256
[SCAN_DBG] Block Count Of Die: 0x1000 // 4096
[SCAN_DBG] Plane Count Of Die: 0x2 // 2
[SCAN_DBG] Die Count Of Chip: 0x1
[SCAN_DBG] Bank Count Of Chip: 0x1
[SCAN_DBG] Optional Operation: 0x21788 //
[SCAN_DBG] Access Frequence: 0x1e // 30
[SCAN_DBG] ECC Mode: 0x5
[SCAN_DBG] Read Retry Type: 0x400a01
^^^^^^^^
ead_retry_mode = (read_retry_type>>16)&0xff; // 40h = Micron
read_retry_cycle =(read_retry_type>>8)&0xff; // 10
read_retry_reg_num = (read_retry_type>>0)&0xff; // 1
Again, if your SPL is flashed correctly you can rely on this info from FEX.
Just to resume and make it finally clear - your SPL, correctly built and
including correct header will load anyway/always, because it is loaded by
BROM (which initializes and works with NAND on this stage). But when SPL
is loaded - you are on your own. Thus SPL has to be configured correctly
to work with appropriate NFC and MTD/NAND or whatever...
"Note that you shouldn't change CONFIG_SPL_TEXT_BASE, like that commit does."
I don't know what exactly in this branch (a20_nand) from this repo helped me
to start U-Boot from NAND (I could not start mainline SPL from NAND nor Proper,
but unfortunately I have no time to prepare whole diff with mainline). But it
works with exactly that value. And I thought that this value is one of the
"magic" of this branch/repo compared to mainline. Did you build SPL (which
you've managed to start from NAND )from mainline or you're using Michał
Motyl repo?
"Could you share these modifications somewhere?"
I was wrong a little bit - it does not read ALL NAND, it just outputs bytes
which are read while loading Proper. Add these lines in sunxi_nand_spl.c to
nand_read_buffer()after ret = nand_read_page(conf, offs, dest, conf->page_size);
#if 0
int j;
for(j = 0; j < conf->page_size; ++j)
{
// if (((((uint8_t*) dest)[j]) >= 32) && ((((uint8_t*) dest)[j]) <= 126 ))
// printf("%c", ((uint8_t*) dest)[j]);
if ((j % 16) == 0 )
printf("\n");
printf("%02x ", ((uint8_t*) dest)[j]);
}
printf("\n\n");
#endifBut if you need to read whole NAND chip I suppose you can just set
CONFIG_SYS_NAND_U_BOOT_OFFS to zero or any offset you wish.
"First bytes of mainline without headers are also "b" instructions (afaik).
The eGON header is useful only for stock boot0, SPL doesn't read it. Jumping
to offset 0 of eGON just skips the header and goes to Proper's own "b"
instructions. No header means no eGON, and jumping straight into Proper."
Of course, you're right. We need correct "B" instruction (as well as header
itself) only for BT0 (because we can't omit BROM). After that if we can flash
Proper without header we don't need it.
P.S.
Yes, you're right. Tested one more time. It looks like FEX recalculates CRC
- 4 bytes next to eGON.BT1 differ with those in my boot1 file. But after that
I see some zeroes (I fill rest of header with zeroes) and the whole page
(2000h bytes - sizeof(header)) filled with FFh (my "alignment") and no
modification. So I don't see what kind of "storage data" is modified by FEX.
(Screenshot attached).
Anyway this should not be the problem - SPL should jump over whole header.
So I still see the ARM "b" instruction as the cause of not starting Proper
even when SPL starts and reads it from standard offset. You can play around
with this with my prints in SPL and see. Maybe on A13 something is different.