[PATCH 2/3] net: sun8i-emac: Always clear syscon EPHY register

[Andre Przywara]

At the moment we only consider the EPHY register for those SoCs were
we actually have an internal PHY to configure. However even other SoCs
have this register, an expect a bit to be cleared for proper operation
with an external PHY.

Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC
model, and clear the H3_EPHY_SELECT bit if no internal PHY is used.

This helps with the upcoming H616 support, were we need to consider two
EMACs.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
---
drivers/net/sun8i_emac.c | 31 +++++++++++++------------------
1 file changed, 13 insertions(+), 18 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 5db33f5c135..a1a30b34579 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -297,30 +297,29 @@ static void sun8i_adjust_link(struct emac_eth_dev *priv,
writel(v, priv->mac_reg + EMAC_CTL0);
}

-static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
+static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
{
if (priv->use_internal_phy) {
/* H3 based SoC's that has an Internal 100MBit PHY
* needs to be configured and powered up before use
*/
- *reg &= ~H3_EPHY_DEFAULT_MASK;
- *reg |= H3_EPHY_DEFAULT_VALUE;
- *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
- *reg &= ~H3_EPHY_SHUTDOWN;
- *reg |= H3_EPHY_SELECT;
- } else
- /* This is to select External Gigabit PHY on
- * the boards with H3 SoC.
- */
- *reg &= ~H3_EPHY_SELECT;
+ reg &= ~H3_EPHY_DEFAULT_MASK;
+ reg |= H3_EPHY_DEFAULT_VALUE;
+ reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
+ reg &= ~H3_EPHY_SHUTDOWN;
+ return reg | H3_EPHY_SELECT;
+ }

- return 0;
+ /* This is to select External Gigabit PHY on those boards with
+ * an internal PHY. Does not hurt on other SoCs. Linux does
+ * it as well.
+ */
+ return reg & ~H3_EPHY_SELECT;
}

static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
struct emac_eth_dev *priv)
{
- int ret;
u32 reg;

if (priv->variant == R40_GMAC) {
@@ -336,11 +335,7 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,

reg = readl(priv->sysctl_reg + 0x30);

- if (priv->variant == H3_EMAC || priv->variant == H6_EMAC) {
- ret = sun8i_emac_set_syscon_ephy(priv, &reg);
- if (ret)
- return ret;
- }
+ reg = sun8i_emac_set_syscon_ephy(priv, reg);

reg &= ~(SC_ETCS_MASK | SC_EPIT);
if (priv->variant == H3_EMAC ||
--
2.17.5

[Andre Przywara]

Hi,

I came up with those three patches to prepare for the H616.
Patch 1 simplifies the MMC driver, so the H616 support becomes a
one-liner.
Patch 2 cleans up the Ethernet driver, so we can support the same
compatible strings and fallbacks as Linux.
Patch 3 prepares the EMAC driver for the second EMAC (100MBit + internal
PHY). We need more code to actually use that PHY, but it's a start to
sort out the different syscon register offset.

Jernej, please feel free to include those in your H616 series, at least
1/3 and 2/3.

Cheers,
Andre

Andre Przywara (3):
mmc: sunxi: Refactor mod clock register offset
net: sun8i-emac: Always clear syscon EPHY register
net: sun8i-emac: Simplify EPHY offset calculation

drivers/mmc/sunxi_mmc.c | 84 +++++++++++-----------------------------
drivers/net/sun8i_emac.c | 43 ++++++++++----------
2 files changed, 44 insertions(+), 83 deletions(-)

--
2.17.5

[Andre Przywara]

So far the only difference between the various Allwinner MMC controller
we are concerned about is the mod clock register offset.
This is actually not directly related to the MMC controller IP, but an
integration choice, dependent on the SoC this appears in.

To avoid becoming trapped with some compatible fallback strings, let's
remove the whole struct sunxi_mmc_variant, and replace this with a SoC
based choice, which we can derive from the CONFIG_MACH_SUNx_y symbols.

This will later simplify H616 support.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
---

drivers/mmc/sunxi_mmc.c | 84 +++++++++++------------------------------
1 file changed, 23 insertions(+), 61 deletions(-)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 0e03b07ce55..bbdbbc7a373 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -23,12 +23,6 @@
#include <asm-generic/gpio.h>
#include <linux/delay.h>

-#ifdef CONFIG_DM_MMC
-struct sunxi_mmc_variant {
- u16 mclk_offset;
-};
-#endif
-
struct sunxi_mmc_plat {
struct mmc_config cfg;
struct mmc mmc;
@@ -42,9 +36,6 @@ struct sunxi_mmc_priv {
int cd_inverted; /* Inverted Card Detect */
struct sunxi_mmc *reg;
struct mmc_config cfg;
-#ifdef CONFIG_DM_MMC
- const struct sunxi_mmc_variant *variant;
-#endif
};

#if !CONFIG_IS_ENABLED(DM_MMC)
@@ -605,6 +596,17 @@ static const struct dm_mmc_ops sunxi_mmc_ops = {
.get_cd = sunxi_mmc_getcd,
};

+static unsigned get_mclk_offset(void)
+{
+ if (IS_ENABLED(CONFIG_MACH_SUN9I_A80))
+ return 0x410;
+
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
+ return 0x830;
+
+ return 0x88;
+};
+
static int sunxi_mmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
@@ -633,8 +635,6 @@ static int sunxi_mmc_probe(struct udevice *dev)
cfg->f_max = 52000000;

priv->reg = (void *)dev_read_addr(dev);
- priv->variant =
- (const struct sunxi_mmc_variant *)dev_get_driver_data(dev);

/* We don't have a sunxi clock driver so find the clock address here */
ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
@@ -644,8 +644,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
ccu_reg = (u32 *)ofnode_get_addr(args.node);

priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
- priv->mclkreg = (void *)ccu_reg +
- (priv->variant->mclk_offset + (priv->mmc_no * 4));
+ priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4;

ret = clk_get_by_name(dev, "ahb", &gate_clk);
if (!ret)
@@ -687,55 +686,18 @@ static int sunxi_mmc_bind(struct udevice *dev)
return mmc_bind(dev, &plat->mmc, &plat->cfg);
}

-static const struct sunxi_mmc_variant sun4i_a10_variant = {
- .mclk_offset = 0x88,
-};
-
-static const struct sunxi_mmc_variant sun9i_a80_variant = {
- .mclk_offset = 0x410,
-};
-
-static const struct sunxi_mmc_variant sun50i_h6_variant = {
- .mclk_offset = 0x830,
-};
-
static const struct udevice_id sunxi_mmc_ids[] = {
- {
- .compatible = "allwinner,sun4i-a10-mmc",
- .data = (ulong)&sun4i_a10_variant,
- },
- {
- .compatible = "allwinner,sun5i-a13-mmc",
- .data = (ulong)&sun4i_a10_variant,
- },
- {
- .compatible = "allwinner,sun7i-a20-mmc",
- .data = (ulong)&sun4i_a10_variant,
- },
- {
- .compatible = "allwinner,sun8i-a83t-emmc",
- .data = (ulong)&sun4i_a10_variant,
- },
- {
- .compatible = "allwinner,sun9i-a80-mmc",
- .data = (ulong)&sun9i_a80_variant,
- },
- {
- .compatible = "allwinner,sun50i-a64-mmc",
- .data = (ulong)&sun4i_a10_variant,
- },
- {
- .compatible = "allwinner,sun50i-a64-emmc",
- .data = (ulong)&sun4i_a10_variant,
- },
- {
- .compatible = "allwinner,sun50i-h6-mmc",
- .data = (ulong)&sun50i_h6_variant,
- },
- {
- .compatible = "allwinner,sun50i-h6-emmc",
- .data = (ulong)&sun50i_h6_variant,
- },
+ { .compatible = "allwinner,sun4i-a10-mmc" },
+ { .compatible = "allwinner,sun5i-a13-mmc" },
+ { .compatible = "allwinner,sun7i-a20-mmc" },
+ { .compatible = "allwinner,sun8i-a83t-emmc" },
+ { .compatible = "allwinner,sun9i-a80-mmc" },
+ { .compatible = "allwinner,sun50i-a64-mmc" },
+ { .compatible = "allwinner,sun50i-a64-emmc" },
+ { .compatible = "allwinner,sun50i-h6-mmc" },
+ { .compatible = "allwinner,sun50i-h6-emmc" },
+ { .compatible = "allwinner,sun50i-a100-mmc" },
+ { .compatible = "allwinner,sun50i-a100-emmc" },
{ /* sentinel */ }
};

--
2.17.5

[Andre Przywara]

Most SoCs using the sun8i-emac IP use a register in the "syscon" area to
control some PHY related settings. The R40 is special, since this
register is located in the CCU IP.
So far we were storing the *base* address in our priv struct, then adding
the offset later when we need to use it.

Change the code to add the offset already when we parse the DT node, so
that sysctl_reg contains the final EPHY register address.
This simplifies adding support for the two EMACs on the H616 later.

Signed-off-by: Andre Przywara <andre.p...@arm.com>
---

drivers/net/sun8i_emac.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index a1a30b34579..38b6b3b08c6 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -324,16 +324,16 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,

if (priv->variant == R40_GMAC) {

/* Select RGMII for R40 */
- reg = readl(priv->sysctl_reg + 0x164);
+ reg = readl(priv->sysctl_reg);
reg |= SC_ETCS_INT_GMII |
SC_EPIT |
(CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);

- writel(reg, priv->sysctl_reg + 0x164);
+ writel(reg, priv->sysctl_reg);
return 0;
}

- reg = readl(priv->sysctl_reg + 0x30);
+ reg = readl(priv->sysctl_reg);

reg = sun8i_emac_set_syscon_ephy(priv, reg);

@@ -374,7 +374,7 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
& SC_ERXDC_MASK;

- writel(reg, priv->sysctl_reg + 0x30);
+ writel(reg, priv->sysctl_reg);

return 0;
}
@@ -916,6 +916,10 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
debug("%s: Cannot find syscon base address\n", __func__);
return -EINVAL;
}
+ if (priv->variant == R40_GMAC)
+ priv->sysctl_reg += 0x164;
+ else
+ priv->sysctl_reg += 0x30;

pdata->phy_interface = -1;
priv->phyaddr = -1;
--
2.17.5

[Jaehoon Chung]

On 1/11/21 10:03 AM, Andre Przywara wrote:
> So far the only difference between the various Allwinner MMC controller
> we are concerned about is the mod clock register offset.
> This is actually not directly related to the MMC controller IP, but an
> integration choice, dependent on the SoC this appears in.
>
> To avoid becoming trapped with some compatible fallback strings, let's
> remove the whole struct sunxi_mmc_variant, and replace this with a SoC
> based choice, which we can derive from the CONFIG_MACH_SUNx_y symbols.
>
> This will later simplify H616 support.
>
> Signed-off-by: Andre Przywara <andre.p...@arm.com>

Reviewed-by: Jaehoon Chung <jh80....@samsung.com>

Best Regards,
Jaehoon Chung

[Jernej Škrabec]

Dne ponedeljek, 11. januar 2021 ob 02:03:03 CET je Andre Przywara napisal(a):

> Hi,
>
> I came up with those three patches to prepare for the H616.
> Patch 1 simplifies the MMC driver, so the H616 support becomes a
> one-liner.
> Patch 2 cleans up the Ethernet driver, so we can support the same
> compatible strings and fallbacks as Linux.
> Patch 3 prepares the EMAC driver for the second EMAC (100MBit + internal
> PHY). We need more code to actually use that PHY, but it's a start to
> sort out the different syscon register offset.
>
> Jernej, please feel free to include those in your H616 series, at least
> 1/3 and 2/3.

Ok, I'll pick patch 1 and 2.

Best regards,
Jernej