[PATCH v5 0/8] Add support for H6 PWM

[Clément Péron]

Hi,

This is a rework of Jernej's previous work[1] taking account all the
previous remarks.

Bindings is still strict but probe in the driver are now optionnals.

If someone could confirm that the PWM is not broken, as my board
doesn't output it.

I didn't add the acked-tags as there are big changes.

Thanks,
Clément

Jernej's cover:
Allwinner H6 SoC has PWM core which is basically the same as that found
in A20, it's just depends on additional bus clock and reset line.

This series adds support for it and extends PWM driver functionality in
a way that it's now possible to bypass whole core and output PWM source
clock directly as a PWM signal. This functionality is needed by AC200
chip, which is bundled in same physical package as H6 SoC, to serve as a
clock source of 24 MHz. AC200 clock input pin is bonded internally to
the second PWM channel.

I would be grateful if anyone can test this patch series for any kind of
regression on other SoCs.

[1]: https://patchwork.kernel.org/cover/11061737/

Changes in v5:
- Move bypass calculation to pwm_calculate
- Split mod_clock fallback from bus_clk probe
- Update comment
- Move my SoB after acked-by/reviewed-by

Changes in v4:
- item description in correct order and add a blank line
- use %pe for printing PTR_ERR
- don't print error when it's an EPROBE_DEFER
- change output clock bypass formula to match PWM policy

Changes in v3:
- Documentation update to allow one clock without name
- Change reset optional to shared
- If reset probe failed return an error
- Remove old clock probe
- Update bypass enabled formula

Changes in v2:
- Remove allOf in Documentation
- Add H6 example in Documentation
- Change clock name from "pwm" to "mod"
- Change reset quirk to optional probe
- Change bus_clock quirk to optional probe
- Add limitation comment about mod_clk_output
- Add quirk for mod_clk_output
- Change bypass formula

Clément Péron (2):
pwm: sun4i: Prefer "mod" clock to unamed
[DO NOT MERGE] arm64: allwinner: h6: enable Beelink GS1 PWM

Jernej Skrabec (6):
dt-bindings: pwm: allwinner: Add H6 PWM description
pwm: sun4i: Add an optional probe for reset line
pwm: sun4i: Add an optional probe for bus clock
pwm: sun4i: Add support to output source clock directly
pwm: sun4i: Add support for H6 PWM
arm64: dts: allwinner: h6: Add PWM node

.../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 48 +++++
.../dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 +
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 +
drivers/pwm/pwm-sun4i.c | 185 +++++++++++++++---
4 files changed, 215 insertions(+), 32 deletions(-)

--
2.20.1

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

H6 PWM block is basically the same as A20 PWM, except that it also has
bus clock and reset line which needs to be handled accordingly.

Expand Allwinner PWM binding with H6 PWM specifics.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Reviewed-by: Rob Herring <ro...@kernel.org>
Signed-off-by: Clément Péron <peron...@gmail.com>
---
.../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 48 +++++++++++++++++++
1 file changed, 48 insertions(+)

diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
index 0ac52f83a58c..1bae446febbb 100644
--- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
@@ -30,13 +30,51 @@ properties:
- items:
- const: allwinner,sun50i-h5-pwm
- const: allwinner,sun5i-a13-pwm
+ - const: allwinner,sun50i-h6-pwm

reg:
maxItems: 1

clocks:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: Module Clock
+ - description: Bus Clock
+
+ # Even though it only applies to subschemas under the conditionals,
+ # not listing them here will trigger a warning because of the
+ # additionalsProperties set to false.
+ clock-names: true
+
+ resets:
maxItems: 1

+ if:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun50i-h6-pwm
+
+ then:
+ properties:
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: mod
+ - const: bus
+
+ required:
+ - clock-names
+ - resets
+
+ else:
+ properties:
+ clocks:
+ maxItems: 1
+
required:
- "#pwm-cells"
- compatible
@@ -54,4 +92,14 @@ examples:
#pwm-cells = <3>;
};

+ - |
+ pwm@300a000 {
+ compatible = "allwinner,sun50i-h6-pwm";
+ reg = <0x0300a000 0x400>;
+ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
+ clock-names = "mod", "bus";
+ resets = <&ccu RST_BUS_PWM>;
+ #pwm-cells = <3>;
+ };
+
...
--
2.20.1

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

H6 PWM core needs deasserted reset line in order to work.

Add an optional probe for it.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Reviewed-by: Uwe Kleine-König <u.klein...@pengutronix.de>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 33 +++++++++++++++++++++++++++++++--
1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 581d23287333..c17935805690 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -16,6 +16,7 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
+#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/time.h>
@@ -78,6 +79,7 @@ struct sun4i_pwm_data {
struct sun4i_pwm_chip {
struct pwm_chip chip;
struct clk *clk;
+ struct reset_control *rst;
void __iomem *base;
spinlock_t ctrl_lock;
const struct sun4i_pwm_data *data;
@@ -364,6 +366,21 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->clk))
return PTR_ERR(pwm->clk);

+ pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
+ if (IS_ERR(pwm->rst)) {
+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "get reset failed %pe\n",
+ pwm->rst);
+ return PTR_ERR(pwm->rst);
+ }
+
+ /* Deassert reset */
+ ret = reset_control_deassert(pwm->rst);
+ if (ret) {
+ dev_err(&pdev->dev, "Cannot deassert reset control\n");
+ return ret;
+ }
+
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;
@@ -376,19 +393,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
ret = pwmchip_add(&pwm->chip);
if (ret < 0) {
dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
- return ret;
+ goto err_pwm_add;
}

platform_set_drvdata(pdev, pwm);

return 0;
+
+err_pwm_add:
+ reset_control_assert(pwm->rst);
+
+ return ret;
}

static int sun4i_pwm_remove(struct platform_device *pdev)
{
struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
+ int ret;
+
+ ret = pwmchip_remove(&pwm->chip);
+ if (ret)
+ return ret;
+
+ reset_control_assert(pwm->rst);

- return pwmchip_remove(&pwm->chip);
+ return 0;
}

static struct platform_driver sun4i_pwm_driver = {
--
2.20.1

[Clément Péron]

New device tree bindings called the source clock of the module
"mod" when several clocks are defined.

Try to get a clock called "mod" if nothing is found try to get
an unnamed clock.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index c17935805690..bbb1ed194c0e 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -362,9 +362,34 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->base))
return PTR_ERR(pwm->base);

- pwm->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(pwm->clk))
+ /*
+ * All hardware variants need a source clock that is divided and
+ * then feeds the counter that defines the output wave form. In the
+ * device tree this clock is either unnamed or called "mod".
+ * Some variants (e.g. H6) need another clock to access the
+ * hardware registers; this is called "bus".
+ * So we request "mod" first (and ignore the corner case that a
+ * parent provides a "mod" clock while the right one would be the
+ * unnamed one of the PWM device) and if this is not found we fall
+ * back to the first clock of the PWM.
+ */
+ pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
+ if (IS_ERR(pwm->clk)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get clock failed %pe\n",
+ pwm->clk);
return PTR_ERR(pwm->clk);
+ }
+
+ if (!pwm->clk) {
+ pwm->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(pwm->clk)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get clock failed %pe\n",
+ pwm->clk);
+ return PTR_ERR(pwm->clk);
+ }

+ }

pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);

if (IS_ERR(pwm->rst)) {
--
2.20.1

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

Now that sun4i PWM driver supports deasserting reset line and enabling
bus clock, support for H6 PWM can be added.

Note that while H6 PWM has two channels, only first one is wired to
output pin. Second channel is used as a clock source to companion AC200
chip which is bundled into same package.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Acked-by: Uwe Kleine-König <u.klein...@pengutronix.de>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index b64250b7e2be..8d6699659db7 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -358,6 +358,12 @@ static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
.npwm = 1,
};

+static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
+ .has_prescaler_bypass = true,
+ .has_direct_mod_clk_output = true,
+ .npwm = 2,
+};
+
static const struct of_device_id sun4i_pwm_dt_ids[] = {
{
.compatible = "allwinner,sun4i-a10-pwm",
@@ -374,6 +380,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = {
}, {
.compatible = "allwinner,sun8i-h3-pwm",
.data = &sun4i_pwm_single_bypass,
+ }, {
+ .compatible = "allwinner,sun50i-h6-pwm",
+ .data = &sun50i_h6_pwm_data,
}, {
/* sentinel */
},
--
2.20.1

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

PWM core has an option to bypass whole logic and output unchanged source
clock as PWM output. This is achieved by enabling bypass bit.

Note that when bypass is enabled, no other setting has any meaning, not
even enable bit.

This mode of operation is needed to achieve high enough frequency to
serve as clock source for AC200 chip which is integrated into same
package as H6 SoC.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 92 ++++++++++++++++++++++++++++-------------
1 file changed, 64 insertions(+), 28 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 93f4d44e9fa8..b64250b7e2be 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -3,6 +3,10 @@
* Driver for Allwinner sun4i Pulse Width Modulation Controller
*
* Copyright (C) 2014 Alexandre Belloni <alexandr...@free-electrons.com>
+ *
+ * Limitations:
+ * - When outputing the source clock directly, the PWM logic will be bypassed
+ * and the currently running period is not guaranteed to be completed
*/

#include <linux/bitops.h>
@@ -73,6 +77,7 @@ static const u32 prescaler_table[] = {

struct sun4i_pwm_data {
bool has_prescaler_bypass;
+ bool has_direct_mod_clk_output;
unsigned int npwm;
};

@@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,

val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

+ /*
+ * PWM chapter in H6 manual has a diagram which explains that if bypass
+ * bit is set, no other setting has any meaning. Even more, experiment
+ * proved that also enable bit is ignored in this case.
+ */
+ if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
+ sun4i_pwm->data->has_direct_mod_clk_output) {
+ state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
+ state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
+ state->polarity = PWM_POLARITY_NORMAL;
+ state->enabled = true;
+ return;
+ }
+
if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
sun4i_pwm->data->has_prescaler_bypass)
prescaler = 1;
@@ -149,13 +168,23 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,

static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
const struct pwm_state *state,
- u32 *dty, u32 *prd, unsigned int *prsclr)
+ u32 *dty, u32 *prd, unsigned int *prsclr,
+ bool *bypass)
{
u64 clk_rate, div = 0;
unsigned int pval, prescaler = 0;

clk_rate = clk_get_rate(sun4i_pwm->clk);

+ *bypass = state->enabled &&
+ (state->period * clk_rate >= NSEC_PER_SEC) &&
+ (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
+ (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
+
+ /* Skip calculation of other parameters if we bypass them */
+ if (*bypass && sun4i_pwm->data->has_direct_mod_clk_output)
+ return 0;
+
if (sun4i_pwm->data->has_prescaler_bypass) {
/* First, test without any prescaler when available */
prescaler = PWM_PRESCAL_MASK;
@@ -202,10 +231,11 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
{
struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
struct pwm_state cstate;
- u32 ctrl;
+ u32 ctrl, period, duty, val;
int ret;
- unsigned int delay_us;
+ unsigned int delay_us, prescaler;
unsigned long now;
+ bool bypass;

pwm_get_state(pwm, &cstate);

@@ -220,43 +250,48 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
spin_lock(&sun4i_pwm->ctrl_lock);
ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

- if ((cstate.period != state->period) ||
- (cstate.duty_cycle != state->duty_cycle)) {
- u32 period, duty, val;
- unsigned int prescaler;
+ ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
+ &bypass);
+ if (ret) {
+ dev_err(chip->dev, "period exceeds the maximum value\n");
+ spin_unlock(&sun4i_pwm->ctrl_lock);
+ if (!cstate.enabled)
+ clk_disable_unprepare(sun4i_pwm->clk);
+ return ret;
+ }

- ret = sun4i_pwm_calculate(sun4i_pwm, state,
- &duty, &period, &prescaler);
- if (ret) {
- dev_err(chip->dev, "period exceeds the maximum value\n");
- spin_unlock(&sun4i_pwm->ctrl_lock);
- if (!cstate.enabled)
- clk_disable_unprepare(sun4i_pwm->clk);
- return ret;
+ if (sun4i_pwm->data->has_direct_mod_clk_output) {
+ if (bypass) {
+ ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
+ /* We can skip apply of other parameters */
+ goto bypass_mode;
+ } else {
+ ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
}
+ }

- if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
- /* Prescaler changed, the clock has to be gated */
- ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
- sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
-
- ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
- ctrl |= BIT_CH(prescaler, pwm->hwpwm);
- }
+ if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
+ /* Prescaler changed, the clock has to be gated */
+ ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
+ sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);

- val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
- sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
- sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
- usecs_to_jiffies(cstate.period / 1000 + 1);
- sun4i_pwm->needs_delay[pwm->hwpwm] = true;
+ ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
+ ctrl |= BIT_CH(prescaler, pwm->hwpwm);
}

+ val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
+ sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
+ sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
+ usecs_to_jiffies(cstate.period / 1000 + 1);
+ sun4i_pwm->needs_delay[pwm->hwpwm] = true;
+
if (state->polarity != PWM_POLARITY_NORMAL)
ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
else
ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);

ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
+
if (state->enabled) {
ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
} else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
@@ -264,6 +299,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
}

+bypass_mode:
sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);

spin_unlock(&sun4i_pwm->ctrl_lock);
--
2.20.1

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

Allwinner H6 PWM is similar to that in A20 except that it has additional

bus clock and reset line.

Note that first PWM channel is connected to output pin and second
channel is used internally, as a clock source to AC200 co-packaged chip.
This means that any combination of these two channels can be used and
thus it doesn't make sense to add pinctrl nodes at this point.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 29824081b43b..6d4bde488f15 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -245,6 +245,16 @@
status = "disabled";
};

+ pwm: pwm@300a000 {

+ compatible = "allwinner,sun50i-h6-pwm";
+ reg = <0x0300a000 0x400>;
+ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
+ clock-names = "mod", "bus";
+ resets = <&ccu RST_BUS_PWM>;
+ #pwm-cells = <3>;

+ status = "disabled";
+ };
+
pio: pinctrl@300b000 {
compatible = "allwinner,sun50i-h6-pinctrl";
reg = <0x0300b000 0x400>;
--
2.20.1

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

H6 PWM core needs bus clock to be enabled in order to work.

Add an optional probe for it and a fallback for previous
bindings without name on module clock.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index bbb1ed194c0e..93f4d44e9fa8 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -78,6 +78,7 @@ struct sun4i_pwm_data {

struct sun4i_pwm_chip {
struct pwm_chip chip;

+ struct clk *bus_clk;
struct clk *clk;

struct reset_control *rst;
void __iomem *base;

@@ -391,6 +392,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
}
}

+ pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
+ if (IS_ERR(pwm->bus_clk)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get bus_clock failed %pe\n",
+ pwm->bus_clk);
+ return PTR_ERR(pwm->bus_clk);

+ }
+
pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
if (IS_ERR(pwm->rst)) {

if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

@@ -406,6 +415,16 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
return ret;
}

+ /*
+ * We're keeping the bus clock on for the sake of simplicity.
+ * Actually it only needs to be on for hardware register accesses.
+ */
+ ret = clk_prepare_enable(pwm->bus_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "Cannot prepare and enable bus_clk\n");
+ goto err_bus;

+ }
+
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;

@@ -426,6 +445,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
return 0;

err_pwm_add:
+ clk_disable_unprepare(pwm->bus_clk);
+err_bus:
reset_control_assert(pwm->rst);

return ret;
@@ -440,6 +461,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev)
if (ret)
return ret;

+ clk_disable_unprepare(pwm->bus_clk);
reset_control_assert(pwm->rst);

return 0;
--
2.20.1

[Clément Péron]

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index f335f7482a73..cf684bc7374d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -136,6 +136,10 @@
vcc-pg-supply = <&reg_aldo1>;
};

+&pwm {
+ status = "okay";
+};
+
&r_i2c {
status = "okay";

--
2.20.1

[Uwe Kleine-König]

I think the line break isn't needed here. Unless I'm mistaken the final
; will end in column 80 which is fine.

> return PTR_ERR(pwm->clk);
> + }
> +
> + if (!pwm->clk) {
> + pwm->clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(pwm->clk)) {
> + if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
> + dev_err(&pdev->dev, "get clock failed %pe\n",
> + pwm->clk);

A different error message than above would be nice to be able to
distinguish the two cases.

Best regards
Uwe

--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |

[Uwe Kleine-König]

On Mon, Nov 18, 2019 at 10:37:23AM +0100, Clément Péron wrote:
> From: Jernej Skrabec <jernej....@siol.net>
>
> H6 PWM core needs bus clock to be enabled in order to work.
>
> Add an optional probe for it and a fallback for previous
> bindings without name on module clock.

This paragraph doesn't belong in this patch's description.

The code changes look fine to me.

[Clément Péron]

Hi,

This is a rework of Jernej's previous work[1] taking account all the
previous remarks.

Bindings is still strict but probe in the driver are now optionnals.

If someone could confirm that the PWM is not broken, as my board
doesn't output it.

I didn't add the acked-tags as there are big changes.

Thanks,
Clément

Jernej's cover:
Allwinner H6 SoC has PWM core which is basically the same as that found
in A20, it's just depends on additional bus clock and reset line.

This series adds support for it and extends PWM driver functionality in
a way that it's now possible to bypass whole core and output PWM source
clock directly as a PWM signal. This functionality is needed by AC200
chip, which is bundled in same physical package as H6 SoC, to serve as a
clock source of 24 MHz. AC200 clock input pin is bonded internally to
the second PWM channel.

I would be grateful if anyone can test this patch series for any kind of
regression on other SoCs.

[1]: https://patchwork.kernel.org/cover/11061737/

Changes in v6:
- Update git commit log
- Distinguish error message

pwm: sun4i: Prefer "mod" clock to unnamed

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

H6 PWM block is basically the same as A20 PWM, except that it also has
bus clock and reset line which needs to be handled accordingly.

Expand Allwinner PWM binding with H6 PWM specifics.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Reviewed-by: Rob Herring <ro...@kernel.org>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

+ pwm@300a000 {

+ compatible = "allwinner,sun50i-h6-pwm";
+ reg = <0x0300a000 0x400>;
+ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
+ clock-names = "mod", "bus";
+ resets = <&ccu RST_BUS_PWM>;
+ #pwm-cells = <3>;

+ };
+
...
--
2.20.1

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

H6 PWM core needs deasserted reset line in order to work.

Add an optional probe for it.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Reviewed-by: Uwe Kleine-König <u.klein...@pengutronix.de>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 33 +++++++++++++++++++++++++++++++--
1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 581d23287333..c17935805690 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c

@@ -16,6 +16,7 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
+#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/time.h>

@@ -78,6 +79,7 @@ struct sun4i_pwm_data {

struct sun4i_pwm_chip {
struct pwm_chip chip;

struct clk *clk;
+ struct reset_control *rst;
void __iomem *base;

spinlock_t ctrl_lock;
const struct sun4i_pwm_data *data;

@@ -364,6 +366,21 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->clk))
return PTR_ERR(pwm->clk);

+ pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
+ if (IS_ERR(pwm->rst)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get reset failed %pe\n",
+ pwm->rst);
+ return PTR_ERR(pwm->rst);
+ }
+
+ /* Deassert reset */
+ ret = reset_control_deassert(pwm->rst);

+ if (ret) {

+ dev_err(&pdev->dev, "Cannot deassert reset control\n");
+ return ret;

+ }
+
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;

@@ -376,19 +393,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
ret = pwmchip_add(&pwm->chip);
if (ret < 0) {
dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
- return ret;
+ goto err_pwm_add;
}

platform_set_drvdata(pdev, pwm);

return 0;
+
+err_pwm_add:
+ reset_control_assert(pwm->rst);
+
+ return ret;
}

static int sun4i_pwm_remove(struct platform_device *pdev)

[Clément Péron]

New device tree bindings called the source clock of the module
"mod" when several clocks are defined.

Try to get a clock called "mod" if nothing is found try to get
an unnamed clock.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index c17935805690..6d97fef4ed43 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c

@@ -362,9 +362,34 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->base))
return PTR_ERR(pwm->base);

- pwm->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(pwm->clk))
+ /*
+ * All hardware variants need a source clock that is divided and
+ * then feeds the counter that defines the output wave form. In the
+ * device tree this clock is either unnamed or called "mod".
+ * Some variants (e.g. H6) need another clock to access the
+ * hardware registers; this is called "bus".
+ * So we request "mod" first (and ignore the corner case that a
+ * parent provides a "mod" clock while the right one would be the
+ * unnamed one of the PWM device) and if this is not found we fall
+ * back to the first clock of the PWM.
+ */
+ pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
+ if (IS_ERR(pwm->clk)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get mod clock failed %pe\n",
+ pwm->clk);

return PTR_ERR(pwm->clk);
+ }
+
+ if (!pwm->clk) {

+ pwm->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(pwm->clk)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get unnamed clock failed %pe\n",

+ pwm->clk);
+ return PTR_ERR(pwm->clk);
+ }

+ }

pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

H6 PWM core needs bus clock to be enabled in order to work.

Add an optional probe for it.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 6d97fef4ed43..ce83d479ba0e 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -78,6 +78,7 @@ struct sun4i_pwm_data {

struct sun4i_pwm_chip {
struct pwm_chip chip;

+ struct clk *bus_clk;
struct clk *clk;

struct reset_control *rst;
void __iomem *base;

@@ -391,6 +392,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
}
}

+ pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
+ if (IS_ERR(pwm->bus_clk)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get bus clock failed %pe\n",

+ pwm->bus_clk);
+ return PTR_ERR(pwm->bus_clk);

+ }
+
pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
if (IS_ERR(pwm->rst)) {

if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

@@ -406,6 +415,16 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
return ret;
}

+ /*
+ * We're keeping the bus clock on for the sake of simplicity.
+ * Actually it only needs to be on for hardware register accesses.
+ */
+ ret = clk_prepare_enable(pwm->bus_clk);

+ if (ret) {

+ dev_err(&pdev->dev, "Cannot prepare and enable bus_clk\n");
+ goto err_bus;

+ }
+
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;

[Clément Péron]

Signed-off-by: Clément Péron <peron...@gmail.com>
---

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

Allwinner H6 PWM is similar to that in A20 except that it has additional

bus clock and reset line.

Note that first PWM channel is connected to output pin and second
channel is used internally, as a clock source to AC200 co-packaged chip.
This means that any combination of these two channels can be used and
thus it doesn't make sense to add pinctrl nodes at this point.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 29824081b43b..6d4bde488f15 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -245,6 +245,16 @@
status = "disabled";
};

+ pwm: pwm@300a000 {

+ compatible = "allwinner,sun50i-h6-pwm";
+ reg = <0x0300a000 0x400>;
+ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
+ clock-names = "mod", "bus";
+ resets = <&ccu RST_BUS_PWM>;
+ #pwm-cells = <3>;

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

PWM core has an option to bypass whole logic and output unchanged source
clock as PWM output. This is achieved by enabling bypass bit.

Note that when bypass is enabled, no other setting has any meaning, not
even enable bit.

This mode of operation is needed to achieve high enough frequency to
serve as clock source for AC200 chip which is integrated into same
package as H6 SoC.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 92 ++++++++++++++++++++++++++++-------------
1 file changed, 64 insertions(+), 28 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index ce83d479ba0e..a1d8851b18f0 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

Now that sun4i PWM driver supports deasserting reset line and enabling
bus clock, support for H6 PWM can be added.

Note that while H6 PWM has two channels, only first one is wired to
output pin. Second channel is used as a clock source to companion AC200
chip which is bundled into same package.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Acked-by: Uwe Kleine-König <u.klein...@pengutronix.de>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index a1d8851b18f0..640f6349e36f 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c

[Clément Péron]

Hi Maxime

On Mon, 18 Nov 2019 at 12:06, Maxime Ripard <mri...@kernel.org> wrote:
>
> Hi,

> Sorry for not noticing this earlier, but this should be at the topmost
> level

No problem, but I don't get what you want, (yaml format is new for me).
Do you mean I should put the if condition before the "resets" ?

Regards,
Clément

>
> Maxime

[Clément Péron]

Hi,

On Mon, 18 Nov 2019 at 13:57, Maxime Ripard <mri...@kernel.org> wrote:

> No, here if we condense a bit the file, we have something like:
>
> title: PWM
>
> properties:
> compatible:
> ...
>
> ...
>
> resets:
> ...
>
> if:
> properties:
> ...
>
> then:
> properties:
> ...
>
> which means that you expect that the node may contain a compatible
> property, a resets one, and then two properties "if" and "then", which
> in turn contain properties (ie, two nodes).
>
> This is obviously not what you want, what you want instead is:
>
> properties:
> compatible:
> ...
>
> ...
>
> resets:
> ...
>
> if:
> properties:
> ...
>
> then:
> properties:
> ...
>
> Which then describes that there's two properties, compatible and
> resets, and if the schema under 'if' is valid against the node we try
> to validate, the schema under 'then' is used to validate the node as
> well.
>
> I hope it's clearer,

Yes it's totally clear didn't see this bad indentation,
Thanks for the catch and for the explanation.

Regards,
Clément

> Maxime

[Clément Péron]

Hi,

This is a rework of Jernej's previous work[1] taking account all the
previous remarks.

Bindings is still strict but probe in the driver are now optionnals.

If someone could confirm that the PWM is not broken, as my board
doesn't output it.

I didn't add the acked-tags as there are big changes.

Thanks,
Clément

Jernej's cover:
Allwinner H6 SoC has PWM core which is basically the same as that found
in A20, it's just depends on additional bus clock and reset line.

This series adds support for it and extends PWM driver functionality in
a way that it's now possible to bypass whole core and output PWM source
clock directly as a PWM signal. This functionality is needed by AC200
chip, which is bundled in same physical package as H6 SoC, to serve as a
clock source of 24 MHz. AC200 clock input pin is bonded internally to
the second PWM channel.

I would be grateful if anyone can test this patch series for any kind of
regression on other SoCs.

[1]: https://patchwork.kernel.org/cover/11061737/

Changes in v7:
- Fix indent in Yaml bindings

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

H6 PWM block is basically the same as A20 PWM, except that it also has
bus clock and reset line which needs to be handled accordingly.

Expand Allwinner PWM binding with H6 PWM specifics.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Reviewed-by: Rob Herring <ro...@kernel.org>
Signed-off-by: Clément Péron <peron...@gmail.com>
---
.../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 48 +++++++++++++++++++
1 file changed, 48 insertions(+)

diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml

index 0ac52f83a58c..a7dc19fc347a 100644

required:
- "#pwm-cells"
- compatible
@@ -54,4 +92,14 @@ examples:
#pwm-cells = <3>;
};

+ - |

+ pwm@300a000 {

+ compatible = "allwinner,sun50i-h6-pwm";
+ reg = <0x0300a000 0x400>;
+ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
+ clock-names = "mod", "bus";
+ resets = <&ccu RST_BUS_PWM>;
+ #pwm-cells = <3>;

+ };
+
...
--
2.20.1

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

H6 PWM core needs deasserted reset line in order to work.

Add an optional probe for it.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Reviewed-by: Uwe Kleine-König <u.klein...@pengutronix.de>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 33 +++++++++++++++++++++++++++++++--
1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 581d23287333..c17935805690 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c

@@ -16,6 +16,7 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
+#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/time.h>

@@ -78,6 +79,7 @@ struct sun4i_pwm_data {

struct sun4i_pwm_chip {
struct pwm_chip chip;

struct clk *clk;
+ struct reset_control *rst;
void __iomem *base;

spinlock_t ctrl_lock;
const struct sun4i_pwm_data *data;
@@ -364,6 +366,21 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->clk))
return PTR_ERR(pwm->clk);

+ pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);

+ if (IS_ERR(pwm->rst)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get reset failed %pe\n",
+ pwm->rst);
+ return PTR_ERR(pwm->rst);
+ }
+
+ /* Deassert reset */
+ ret = reset_control_deassert(pwm->rst);

+ if (ret) {

+ dev_err(&pdev->dev, "Cannot deassert reset control\n");
+ return ret;

+ }
+
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;

@@ -376,19 +393,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
ret = pwmchip_add(&pwm->chip);
if (ret < 0) {
dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
- return ret;
+ goto err_pwm_add;
}

platform_set_drvdata(pdev, pwm);

return 0;
+
+err_pwm_add:
+ reset_control_assert(pwm->rst);
+
+ return ret;
}

static int sun4i_pwm_remove(struct platform_device *pdev)

[Clément Péron]

New device tree bindings called the source clock of the module
"mod" when several clocks are defined.

Try to get a clock called "mod" if nothing is found try to get
an unnamed clock.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index c17935805690..6d97fef4ed43 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c

@@ -362,9 +362,34 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->base))
return PTR_ERR(pwm->base);

- pwm->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(pwm->clk))
+ /*
+ * All hardware variants need a source clock that is divided and
+ * then feeds the counter that defines the output wave form. In the
+ * device tree this clock is either unnamed or called "mod".
+ * Some variants (e.g. H6) need another clock to access the
+ * hardware registers; this is called "bus".
+ * So we request "mod" first (and ignore the corner case that a
+ * parent provides a "mod" clock while the right one would be the
+ * unnamed one of the PWM device) and if this is not found we fall
+ * back to the first clock of the PWM.
+ */
+ pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
+ if (IS_ERR(pwm->clk)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get mod clock failed %pe\n",
+ pwm->clk);
return PTR_ERR(pwm->clk);
+ }
+
+ if (!pwm->clk) {

+ pwm->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(pwm->clk)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get unnamed clock failed %pe\n",
+ pwm->clk);
+ return PTR_ERR(pwm->clk);
+ }

+ }

pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

H6 PWM core needs bus clock to be enabled in order to work.

Add an optional probe for it.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 6d97fef4ed43..ce83d479ba0e 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -78,6 +78,7 @@ struct sun4i_pwm_data {

struct sun4i_pwm_chip {
struct pwm_chip chip;

+ struct clk *bus_clk;
struct clk *clk;

struct reset_control *rst;
void __iomem *base;

@@ -391,6 +392,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
}
}

+ pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
+ if (IS_ERR(pwm->bus_clk)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get bus clock failed %pe\n",
+ pwm->bus_clk);
+ return PTR_ERR(pwm->bus_clk);

+ }
+
pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
if (IS_ERR(pwm->rst)) {

if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

@@ -406,6 +415,16 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
return ret;
}

+ /*
+ * We're keeping the bus clock on for the sake of simplicity.
+ * Actually it only needs to be on for hardware register accesses.
+ */
+ ret = clk_prepare_enable(pwm->bus_clk);

+ if (ret) {

+ dev_err(&pdev->dev, "Cannot prepare and enable bus_clk\n");
+ goto err_bus;

+ }
+
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

PWM core has an option to bypass whole logic and output unchanged source
clock as PWM output. This is achieved by enabling bypass bit.

Note that when bypass is enabled, no other setting has any meaning, not
even enable bit.

This mode of operation is needed to achieve high enough frequency to
serve as clock source for AC200 chip which is integrated into same
package as H6 SoC.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 92 ++++++++++++++++++++++++++++-------------
1 file changed, 64 insertions(+), 28 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index ce83d479ba0e..a1d8851b18f0 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

Now that sun4i PWM driver supports deasserting reset line and enabling
bus clock, support for H6 PWM can be added.

Note that while H6 PWM has two channels, only first one is wired to
output pin. Second channel is used as a clock source to companion AC200
chip which is bundled into same package.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Acked-by: Uwe Kleine-König <u.klein...@pengutronix.de>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index a1d8851b18f0..640f6349e36f 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

Allwinner H6 PWM is similar to that in A20 except that it has additional

bus clock and reset line.

Note that first PWM channel is connected to output pin and second
channel is used internally, as a clock source to AC200 co-packaged chip.
This means that any combination of these two channels can be used and
thus it doesn't make sense to add pinctrl nodes at this point.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 29824081b43b..6d4bde488f15 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -245,6 +245,16 @@
status = "disabled";
};

+ pwm: pwm@300a000 {

+ compatible = "allwinner,sun50i-h6-pwm";
+ reg = <0x0300a000 0x400>;
+ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
+ clock-names = "mod", "bus";
+ resets = <&ccu RST_BUS_PWM>;
+ #pwm-cells = <3>;

[Clément Péron]

Signed-off-by: Clément Péron <peron...@gmail.com>
---

[Uwe Kleine-König]

On Tue, Nov 19, 2019 at 06:53:14PM +0100, Clément Péron wrote:
> New device tree bindings called the source clock of the module
> "mod" when several clocks are defined.
>
> Try to get a clock called "mod" if nothing is found try to get
> an unnamed clock.
>
> Signed-off-by: Clément Péron <peron...@gmail.com>

Reviewed-by: Uwe Kleine-König <u.klein...@pengutronix.de>

Thanks

[Uwe Kleine-König]

Hello Clément,

On Tue, Nov 19, 2019 at 06:53:15PM +0100, Clément Péron wrote:
> + /*
> + * We're keeping the bus clock on for the sake of simplicity.
> + * Actually it only needs to be on for hardware register accesses.
> + */
> + ret = clk_prepare_enable(pwm->bus_clk);
> + if (ret) {
> + dev_err(&pdev->dev, "Cannot prepare and enable bus_clk\n");

Maybe add the error code to the message?

Best regards

[Uwe Kleine-König]

Hello Clément,

Hmm, so if my PWM doesn't support the bypass bit *bypass might still be
true on return of sun4i_pwm_calculate. It doesn't hurt because the value
is only used after another check of has_direct_mod_clk_output, but still
this is a bit confusing.

This would be a bit easier to review if this commit was split into two
patches. One that drops the check for cstate.period != state->period etc
(which otherwise is nearly empty when ignoring whitespace changes), and
a second that then adds bypass support.

> + if (sun4i_pwm->data->has_direct_mod_clk_output) {
> + if (bypass) {
> + ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
> + /* We can skip apply of other parameters */
> + goto bypass_mode;

I would prefer to use goto only for error handling. Not sure if there is
a nice way to do that.

> + } else {
> + ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
> }
> + }

[Clément Péron]

Hi Uwe,

On Thu, 21 Nov 2019 at 08:28, Uwe Kleine-König
<u.klein...@pengutronix.de> wrote:
>
> Hello Clément,
>
> On Tue, Nov 19, 2019 at 06:53:15PM +0100, Clément Péron wrote:
> > + /*
> > + * We're keeping the bus clock on for the sake of simplicity.
> > + * Actually it only needs to be on for hardware register accesses.
> > + */
> > + ret = clk_prepare_enable(pwm->bus_clk);
> > + if (ret) {
> > + dev_err(&pdev->dev, "Cannot prepare and enable bus_clk\n");
>
> Maybe add the error code to the message?

Ok I will change it for the reset control deassert if you agree.

Clement

[Clément Péron]

Hi Uwe,

Ok will change this

>
> > if (sun4i_pwm->data->has_prescaler_bypass) {
> > /* First, test without any prescaler when available */
> > prescaler = PWM_PRESCAL_MASK;
> > @@ -202,10 +231,11 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> > {
> > struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
> > struct pwm_state cstate;
> > - u32 ctrl;
> > + u32 ctrl, period, duty, val;
> > int ret;
> > - unsigned int delay_us;
> > + unsigned int delay_us, prescaler;
> > unsigned long now;
> > + bool bypass;
> >
> > pwm_get_state(pwm, &cstate);
> >
> > @@ -220,43 +250,48 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> > spin_lock(&sun4i_pwm->ctrl_lock);
> > ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
> >
> > - if ((cstate.period != state->period) ||
> > - (cstate.duty_cycle != state->duty_cycle)) {
> > - u32 period, duty, val;

> > - unsigned int prescaler;n write the register and return
But

> > + ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
> > + &bypass);
> > + if (ret) {
> > + dev_err(chip->dev, "period exceeds the maximum value\n");
> > + spin_unlock(&sun4i_pwm->ctrl_lock);
> > + if (!cstate.enabled)
> > + clk_disable_unprepare(sun4i_pwm->clk);
> > + return ret;
> > + }
> >
> > - ret = sun4i_pwm_calculate(sun4i_pwm, state,
> > - &duty, &period, &prescaler);
> > - if (ret) {
> > - dev_err(chip->dev, "period exceeds the maximum value\n");
> > - spin_unlock(&sun4i_pwm->ctrl_lock);
> > - if (!cstate.enabled)
> > - clk_disable_unprepare(sun4i_pwm->clk);
> > - return ret;
>
> This would be a bit easier to review if this commit was split into two
> patches. One that drops the check for cstate.period != state->period etc
> (which otherwise is nearly empty when ignoring whitespace changes), and
> a second that then adds bypass support.

Ok

>
>
> > + if (sun4i_pwm->data->has_direct_mod_clk_output) {
> > + if (bypass) {
> > + ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
> > + /* We can skip apply of other parameters */
> > + goto bypass_mode;
>
> I would prefer to use goto only for error handling. Not sure if there is
> a nice way to do that.

As the PWM is necessarily enabled we can write the register and return
but not sure it's more proper.

sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
spin_unlock(&sun4i_pwm->ctrl_lock);

return 0;

Regards,
Clément

[Clément Péron]

Hi,

This is a rework of Jernej's previous work[1] taking account all the
previous remarks.

Bindings is still strict but probe in the driver are now optionnals.

If someone could confirm that the PWM is not broken, as my board
doesn't output it.

Thanks,
Clément

Jernej's cover:
Allwinner H6 SoC has PWM core which is basically the same as that found
in A20, it's just depends on additional bus clock and reset line.

This series adds support for it and extends PWM driver functionality in
a way that it's now possible to bypass whole core and output PWM source
clock directly as a PWM signal. This functionality is needed by AC200
chip, which is bundled in same physical package as H6 SoC, to serve as a
clock source of 24 MHz. AC200 clock input pin is bonded internally to
the second PWM channel.

I would be grateful if anyone can test this patch series for any kind of
regression on other SoCs.

[1]: https://patchwork.kernel.org/cover/11061737/

Changes in v8:
- Display error return code
- split commit
- bypass is false if unsupported
- return instead of goto

pwm: sun4i: Always calculate params when applying new parameters

Jernej Skrabec (4):

pwm: sun4i: Add an optional probe for reset line
pwm: sun4i: Add an optional probe for bus clock
pwm: sun4i: Add support to output source clock directly
pwm: sun4i: Add support for H6 PWM

drivers/pwm/pwm-sun4i.c | 187 +++++++++++++++++++++++++++++++++-------
1 file changed, 156 insertions(+), 31 deletions(-)

--
2.20.1

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

H6 PWM core needs deasserted reset line in order to work.

Add an optional probe for it.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Reviewed-by: Uwe Kleine-König <u.klein...@pengutronix.de>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 34 ++++++++++++++++++++++++++++++++--
1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 581d23287333..e353a03ec614 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c

@@ -16,6 +16,7 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
+#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/time.h>

@@ -78,6 +79,7 @@ struct sun4i_pwm_data {

struct sun4i_pwm_chip {
struct pwm_chip chip;

struct clk *clk;
+ struct reset_control *rst;
void __iomem *base;

spinlock_t ctrl_lock;
const struct sun4i_pwm_data *data;

@@ -364,6 +366,22 @@ static int sun4i_pwm_probe(struct platform_device *pdev)

if (IS_ERR(pwm->clk))
return PTR_ERR(pwm->clk);

+ pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);

+ if (IS_ERR(pwm->rst)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get reset failed %pe\n",
+ pwm->rst);
+ return PTR_ERR(pwm->rst);
+ }
+
+ /* Deassert reset */
+ ret = reset_control_deassert(pwm->rst);

+ if (ret) {
+ dev_err(&pdev->dev, "Cannot deassert reset control: %d\n",
+ ret);
+ return ret;

+ }
+
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;

@@ -376,19 +394,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev)

ret = pwmchip_add(&pwm->chip);
if (ret < 0) {
dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
- return ret;
+ goto err_pwm_add;
}

platform_set_drvdata(pdev, pwm);

return 0;
+
+err_pwm_add:
+ reset_control_assert(pwm->rst);
+
+ return ret;
}

static int sun4i_pwm_remove(struct platform_device *pdev)

[Clément Péron]

New device tree bindings called the source clock of the module
"mod" when several clocks are defined.

Try to get a clock called "mod" if nothing is found try to get
an unnamed clock.

Reviewed-by: Uwe Kleine-König <u.klein...@pengutronix.de>
Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index e353a03ec614..369990ae7d09 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c

@@ -362,9 +362,34 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->base))
return PTR_ERR(pwm->base);

- pwm->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(pwm->clk))
+ /*
+ * All hardware variants need a source clock that is divided and
+ * then feeds the counter that defines the output wave form. In the
+ * device tree this clock is either unnamed or called "mod".
+ * Some variants (e.g. H6) need another clock to access the
+ * hardware registers; this is called "bus".
+ * So we request "mod" first (and ignore the corner case that a
+ * parent provides a "mod" clock while the right one would be the
+ * unnamed one of the PWM device) and if this is not found we fall
+ * back to the first clock of the PWM.
+ */
+ pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
+ if (IS_ERR(pwm->clk)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get mod clock failed %pe\n",
+ pwm->clk);
return PTR_ERR(pwm->clk);
+ }
+
+ if (!pwm->clk) {

+ pwm->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(pwm->clk)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get unnamed clock failed %pe\n",
+ pwm->clk);
+ return PTR_ERR(pwm->clk);
+ }

+ }

pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

H6 PWM core needs bus clock to be enabled in order to work.

Add an optional probe for it.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 369990ae7d09..66befd8d6f9c 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -78,6 +78,7 @@ struct sun4i_pwm_data {

struct sun4i_pwm_chip {
struct pwm_chip chip;

+ struct clk *bus_clk;
struct clk *clk;

struct reset_control *rst;
void __iomem *base;

@@ -391,6 +392,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
}
}

+ pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
+ if (IS_ERR(pwm->bus_clk)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get bus clock failed %pe\n",
+ pwm->bus_clk);
+ return PTR_ERR(pwm->bus_clk);

+ }
+
pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
if (IS_ERR(pwm->rst)) {

if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

@@ -407,6 +416,17 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
return ret;

}

+ /*
+ * We're keeping the bus clock on for the sake of simplicity.
+ * Actually it only needs to be on for hardware register accesses.
+ */
+ ret = clk_prepare_enable(pwm->bus_clk);

+ if (ret) {
+ dev_err(&pdev->dev, "Cannot prepare and enable bus_clk %d\n",
+ ret);
+ goto err_bus;

+ }
+
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;

@@ -427,6 +447,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev)

return 0;

err_pwm_add:
+ clk_disable_unprepare(pwm->bus_clk);
+err_bus:
reset_control_assert(pwm->rst);

return ret;

@@ -441,6 +463,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev)

[Clément Péron]

Bypass mode will require to be re-calculated when the pwm state
is changed.

Remove the condition so pwm_sun4i_calculate is always called.

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 52 ++++++++++++++++++-----------------------
1 file changed, 23 insertions(+), 29 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 66befd8d6f9c..1fa2057419fb 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -202,9 +202,9 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,

{
struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
struct pwm_state cstate;
- u32 ctrl;

+ u32 ctrl, duty, period, val;

int ret;
- unsigned int delay_us;
+ unsigned int delay_us, prescaler;
unsigned long now;

pwm_get_state(pwm, &cstate);
@@ -220,43 +220,37 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,

spin_lock(&sun4i_pwm->ctrl_lock);
ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

- if ((cstate.period != state->period) ||
- (cstate.duty_cycle != state->duty_cycle)) {
- u32 period, duty, val;
- unsigned int prescaler;

-

- ret = sun4i_pwm_calculate(sun4i_pwm, state,
- &duty, &period, &prescaler);
- if (ret) {
- dev_err(chip->dev, "period exceeds the maximum value\n");
- spin_unlock(&sun4i_pwm->ctrl_lock);
- if (!cstate.enabled)
- clk_disable_unprepare(sun4i_pwm->clk);
- return ret;

- }
-

- if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
- /* Prescaler changed, the clock has to be gated */
- ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
- sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);

+ ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler);

+ if (ret) {
+ dev_err(chip->dev, "period exceeds the maximum value\n");
+ spin_unlock(&sun4i_pwm->ctrl_lock);
+ if (!cstate.enabled)
+ clk_disable_unprepare(sun4i_pwm->clk);
+ return ret;
+ }

--
2.20.1

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

PWM core has an option to bypass whole logic and output unchanged source
clock as PWM output. This is achieved by enabling bypass bit.

Note that when bypass is enabled, no other setting has any meaning, not
even enable bit.

This mode of operation is needed to achieve high enough frequency to
serve as clock source for AC200 chip which is integrated into same
package as H6 SoC.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 48 +++++++++++++++++++++++++++++++++++++++--
1 file changed, 46 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 1fa2057419fb..0fe9c680d6d0 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c

@@ -149,13 +168,24 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,

static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
const struct pwm_state *state,
- u32 *dty, u32 *prd, unsigned int *prsclr)
+ u32 *dty, u32 *prd, unsigned int *prsclr,
+ bool *bypass)
{
u64 clk_rate, div = 0;
unsigned int pval, prescaler = 0;

clk_rate = clk_get_rate(sun4i_pwm->clk);

+ *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
+ state->enabled &&

+ (state->period * clk_rate >= NSEC_PER_SEC) &&
+ (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
+ (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
+
+ /* Skip calculation of other parameters if we bypass them */

+ if (*bypass)
+ return 0;
+

if (sun4i_pwm->data->has_prescaler_bypass) {
/* First, test without any prescaler when available */
prescaler = PWM_PRESCAL_MASK;

@@ -206,6 +236,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
int ret;

unsigned int delay_us, prescaler;
unsigned long now;

+ bool bypass;

pwm_get_state(pwm, &cstate);

@@ -220,7 +251,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,

spin_lock(&sun4i_pwm->ctrl_lock);
ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

- ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler);
+ ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
+ &bypass);
if (ret) {

dev_err(chip->dev, "period exceeds the maximum value\n");

spin_unlock(&sun4i_pwm->ctrl_lock);
@@ -229,6 +261,18 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
return ret;

}

+ if (sun4i_pwm->data->has_direct_mod_clk_output) {
+ if (bypass) {
+ ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);

+ /* We can skip other parameter */
+ sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
+ spin_unlock(&sun4i_pwm->ctrl_lock);
+ return 0;

+ } else {
+ ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
+ }

+ }

+
if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {

/* Prescaler changed, the clock has to be gated */

ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);

--
2.20.1

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

Now that sun4i PWM driver supports deasserting reset line and enabling
bus clock, support for H6 PWM can be added.

Note that while H6 PWM has two channels, only first one is wired to
output pin. Second channel is used as a clock source to companion AC200
chip which is bundled into same package.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Acked-by: Uwe Kleine-König <u.klein...@pengutronix.de>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 0fe9c680d6d0..84f3ccab47f9 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -360,6 +360,12 @@ static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {

.npwm = 1,
};

+static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
+ .has_prescaler_bypass = true,
+ .has_direct_mod_clk_output = true,
+ .npwm = 2,
+};
+
static const struct of_device_id sun4i_pwm_dt_ids[] = {
{
.compatible = "allwinner,sun4i-a10-pwm",

@@ -376,6 +382,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = {

[Uwe Kleine-König]

nitpick: other error messages in this driver start with a lower case
letter.

Until there is an equivalent for %pe that consumes an int, I suggest to
use

dev_err(&pdev->dev, "Cannot prepare and enable bus_clk: %pe\n",
ERR_PTR(ret));

to benefit from a symbolic error name instead of an error constant.

[Uwe Kleine-König]

On Thu, Nov 21, 2019 at 08:59:00PM +0100, Clément Péron wrote:
> Bypass mode will require to be re-calculated when the pwm state
> is changed.
>
> Remove the condition so pwm_sun4i_calculate is always called.
>
> Signed-off-by: Clément Péron <peron...@gmail.com>

When applying this patch and looking at it using git show -b it is
obvious the patch does exactly what is promised here. (Apart from the
introduced empty line in the last hunk which is ok in my book.)

Reviewed-by: Uwe Kleine-König <u.klein...@pengutronix.de>

Thanks

[Uwe Kleine-König]

This could be simplified to:

if (bypass) {

ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);

/*
* Other parameters are not relevant in this mode and so
* writing them can be skipped
*/

sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
spin_unlock(&sun4i_pwm->ctrl_lock);
return 0;

} else {

ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
}

which has the advantage(?) that the bypass bit is also (more obviously)
cleared for SoCs that don't support it and it reduces the indention
level.

Best regards

[Clément Péron]

Hi Uwe,

This bit is not guaranteed to be reserved for all the SoC variants.

I don't think it's a good idea to set to 0 a bit which is undefined.

Regards,
Clement

[Clément Péron]

Hi Uwe,

Ok i will fix both

Thanks,
Clement

[Clément Péron]

Hi Uwe,

Let me know if you agree or not with this and I send the v9 according
to your answer.

Regards,
Clément

[Uwe Kleine-König]

If my suggestion is not safe according to the documentation, it is
obviously wrong. So only take it into account if a zero can be safely
written.

[Clément Péron]

Hi,

This is a rework of Jernej's previous work[1] taking account all the
previous remarks.

Bindings is still strict but probe in the driver are now optionnals.

If someone could confirm that the PWM is not broken, as my board
doesn't output it.

Thanks,
Clément

Jernej's cover:
Allwinner H6 SoC has PWM core which is basically the same as that found
in A20, it's just depends on additional bus clock and reset line.

This series adds support for it and extends PWM driver functionality in
a way that it's now possible to bypass whole core and output PWM source
clock directly as a PWM signal. This functionality is needed by AC200
chip, which is bundled in same physical package as H6 SoC, to serve as a
clock source of 24 MHz. AC200 clock input pin is bonded internally to
the second PWM channel.

I would be grateful if anyone can test this patch series for any kind of
regression on other SoCs.

[1]: https://patchwork.kernel.org/cover/11061737/

Changes in v9:
- print error code in error message
- no capital letter to keep coherency

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

H6 PWM core needs deasserted reset line in order to work.

Add an optional probe for it.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Reviewed-by: Uwe Kleine-König <u.klein...@pengutronix.de>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 34 ++++++++++++++++++++++++++++++++--
1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 581d23287333..487899d4cc3f 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c

@@ -16,6 +16,7 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
+#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/time.h>

@@ -78,6 +79,7 @@ struct sun4i_pwm_data {

struct sun4i_pwm_chip {
struct pwm_chip chip;

struct clk *clk;
+ struct reset_control *rst;
void __iomem *base;

spinlock_t ctrl_lock;
const struct sun4i_pwm_data *data;
@@ -364,6 +366,22 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->clk))
return PTR_ERR(pwm->clk);

+ pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);

+ if (IS_ERR(pwm->rst)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get reset failed %pe\n",
+ pwm->rst);
+ return PTR_ERR(pwm->rst);
+ }
+
+ /* Deassert reset */
+ ret = reset_control_deassert(pwm->rst);

+ if (ret) {
+ dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
+ ERR_PTR(ret));
+ return ret;

+ }
+
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;

@@ -376,19 +394,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
ret = pwmchip_add(&pwm->chip);
if (ret < 0) {
dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
- return ret;
+ goto err_pwm_add;
}

platform_set_drvdata(pdev, pwm);

return 0;
+
+err_pwm_add:
+ reset_control_assert(pwm->rst);
+
+ return ret;
}

static int sun4i_pwm_remove(struct platform_device *pdev)

[Clément Péron]

New device tree bindings called the source clock of the module
"mod" when several clocks are defined.

Try to get a clock called "mod" if nothing is found try to get
an unnamed clock.

Reviewed-by: Uwe Kleine-König <u.klein...@pengutronix.de>
Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 487899d4cc3f..80026167044b 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c

@@ -362,9 +362,34 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->base))
return PTR_ERR(pwm->base);

- pwm->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(pwm->clk))
+ /*
+ * All hardware variants need a source clock that is divided and
+ * then feeds the counter that defines the output wave form. In the
+ * device tree this clock is either unnamed or called "mod".
+ * Some variants (e.g. H6) need another clock to access the
+ * hardware registers; this is called "bus".
+ * So we request "mod" first (and ignore the corner case that a
+ * parent provides a "mod" clock while the right one would be the
+ * unnamed one of the PWM device) and if this is not found we fall
+ * back to the first clock of the PWM.
+ */
+ pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
+ if (IS_ERR(pwm->clk)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get mod clock failed %pe\n",
+ pwm->clk);
return PTR_ERR(pwm->clk);
+ }
+
+ if (!pwm->clk) {

+ pwm->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(pwm->clk)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get unnamed clock failed %pe\n",
+ pwm->clk);
+ return PTR_ERR(pwm->clk);
+ }

+ }

pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

H6 PWM core needs bus clock to be enabled in order to work.

Add an optional probe for it.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 80026167044b..a6727dd89e28 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -78,6 +78,7 @@ struct sun4i_pwm_data {

struct sun4i_pwm_chip {
struct pwm_chip chip;

+ struct clk *bus_clk;
struct clk *clk;

struct reset_control *rst;
void __iomem *base;

@@ -391,6 +392,14 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
}
}

+ pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
+ if (IS_ERR(pwm->bus_clk)) {

+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

+ dev_err(&pdev->dev, "get bus clock failed %pe\n",
+ pwm->bus_clk);
+ return PTR_ERR(pwm->bus_clk);

+ }
+
pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
if (IS_ERR(pwm->rst)) {

if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)

@@ -407,6 +416,17 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
return ret;
}

+ /*
+ * We're keeping the bus clock on for the sake of simplicity.
+ * Actually it only needs to be on for hardware register accesses.
+ */
+ ret = clk_prepare_enable(pwm->bus_clk);

+ if (ret) {
+ dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
+ ERR_PTR(ret));
+ goto err_bus;

+ }
+
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;

[Clément Péron]

Bypass mode will require to be re-calculated when the pwm state
is changed.

Remove the condition so pwm_sun4i_calculate is always called.

Reviewed-by: Uwe Kleine-König <u.klein...@pengutronix.de>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 52 ++++++++++++++++++-----------------------
1 file changed, 23 insertions(+), 29 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index a6727dd89e28..e369b5a398f4 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c

@@ -202,9 +202,9 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
{
struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
struct pwm_state cstate;
- u32 ctrl;
+ u32 ctrl, duty, period, val;
int ret;
- unsigned int delay_us;

+ unsigned int delay_us, prescaler;
unsigned long now;

pwm_get_state(pwm, &cstate);
@@ -220,43 +220,37 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,

spin_lock(&sun4i_pwm->ctrl_lock);
ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

- if ((cstate.period != state->period) ||
- (cstate.duty_cycle != state->duty_cycle)) {
- u32 period, duty, val;
- unsigned int prescaler;
-

- ret = sun4i_pwm_calculate(sun4i_pwm, state,

- &duty, &period, &prescaler);
- if (ret) {
- dev_err(chip->dev, "period exceeds the maximum value\n");
- spin_unlock(&sun4i_pwm->ctrl_lock);
- if (!cstate.enabled)
- clk_disable_unprepare(sun4i_pwm->clk);
- return ret;
- }
-
- if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
- /* Prescaler changed, the clock has to be gated */
- ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
- sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
+ ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler);
+ if (ret) {
+ dev_err(chip->dev, "period exceeds the maximum value\n");
+ spin_unlock(&sun4i_pwm->ctrl_lock);
+ if (!cstate.enabled)
+ clk_disable_unprepare(sun4i_pwm->clk);
+ return ret;
+ }

- ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
- ctrl |= BIT_CH(prescaler, pwm->hwpwm);
- }

+ if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

PWM core has an option to bypass whole logic and output unchanged source
clock as PWM output. This is achieved by enabling bypass bit.

Note that when bypass is enabled, no other setting has any meaning, not
even enable bit.

This mode of operation is needed to achieve high enough frequency to
serve as clock source for AC200 chip which is integrated into same
package as H6 SoC.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 48 +++++++++++++++++++++++++++++++++++++++--
1 file changed, 46 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index e369b5a398f4..07bf7be6074b 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c

@@ -206,6 +236,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
int ret;

unsigned int delay_us, prescaler;
unsigned long now;

+ bool bypass;

pwm_get_state(pwm, &cstate);

@@ -220,7 +251,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,

spin_lock(&sun4i_pwm->ctrl_lock);
ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

- ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler);
+ ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
+ &bypass);
if (ret) {

dev_err(chip->dev, "period exceeds the maximum value\n");

spin_unlock(&sun4i_pwm->ctrl_lock);
@@ -229,6 +261,18 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
return ret;
}

+ if (sun4i_pwm->data->has_direct_mod_clk_output) {
+ if (bypass) {
+ ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
+ /* We can skip other parameter */
+ sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
+ spin_unlock(&sun4i_pwm->ctrl_lock);
+ return 0;
+ } else {
+ ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
+ }
+ }

+
if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {

/* Prescaler changed, the clock has to be gated */

ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);

--
2.20.1

[Clément Péron]

From: Jernej Skrabec <jernej....@siol.net>

Now that sun4i PWM driver supports deasserting reset line and enabling
bus clock, support for H6 PWM can be added.

Note that while H6 PWM has two channels, only first one is wired to
output pin. Second channel is used as a clock source to companion AC200
chip which is bundled into same package.

Signed-off-by: Jernej Skrabec <jernej....@siol.net>
Acked-by: Uwe Kleine-König <u.klein...@pengutronix.de>

Signed-off-by: Clément Péron <peron...@gmail.com>
---

drivers/pwm/pwm-sun4i.c | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 07bf7be6074b..c394878c7e5d 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c

[Uwe Kleine-König]

On Sun, Nov 24, 2019 at 06:29:05PM +0100, Clément Péron wrote:
> From: Jernej Skrabec <jernej....@siol.net>
>
> H6 PWM core needs bus clock to be enabled in order to work.
>
> Add an optional probe for it.
>
> Signed-off-by: Jernej Skrabec <jernej....@siol.net>
> Signed-off-by: Clément Péron <peron...@gmail.com>

Reviewed-by: Uwe Kleine-König <u.klein...@pengutronix.de>

Thanks

[Uwe Kleine-König]

Hello Clément,

On Sun, Nov 24, 2019 at 06:29:07PM +0100, Clément Péron wrote:
> From: Jernej Skrabec <jernej....@siol.net>
>
> PWM core has an option to bypass whole logic and output unchanged source
> clock as PWM output. This is achieved by enabling bypass bit.
>
> Note that when bypass is enabled, no other setting has any meaning, not
> even enable bit.
>
> This mode of operation is needed to achieve high enough frequency to
> serve as clock source for AC200 chip which is integrated into same
> package as H6 SoC.
>
> Signed-off-by: Jernej Skrabec <jernej....@siol.net>
> Signed-off-by: Clément Péron <peron...@gmail.com>

This looks fine now,

[Rob Herring]

On Thu, Nov 21, 2019 at 1:24 AM Maxime Ripard <max...@cerno.tech> wrote:

>
> On Tue, Nov 19, 2019 at 06:53:11PM +0100, Clément Péron wrote:
> > Hi,
> >
> > This is a rework of Jernej's previous work[1] taking account all the
> > previous remarks.
> >
> > Bindings is still strict but probe in the driver are now optionnals.
> >
> > If someone could confirm that the PWM is not broken, as my board
> > doesn't output it.
> >

> > I didn't add the acked-tags as there are big changes.
>
> Applied 1 and 7 for 5.6, thanks!

I believe patch 7 breaks linux-next:

Error: Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.example.dts:35.37-38
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.example.dt.yaml]
Error 1

Usually that's due to a missing include.

Rob

[Clément Péron]

Hi Rob,

On Tue, 10 Dec 2019 at 17:48, Rob Herring <rob...@kernel.org> wrote:
>
> On Thu, Nov 21, 2019 at 1:24 AM Maxime Ripard <max...@cerno.tech> wrote:
> >
> > On Tue, Nov 19, 2019 at 06:53:11PM +0100, Clément Péron wrote:
> > > Hi,
> > >
> > > This is a rework of Jernej's previous work[1] taking account all the
> > > previous remarks.
> > >
> > > Bindings is still strict but probe in the driver are now optionnals.
> > >
> > > If someone could confirm that the PWM is not broken, as my board
> > > doesn't output it.
> > >
> > > I didn't add the acked-tags as there are big changes.
> >
> > Applied 1 and 7 for 5.6, thanks!
>
> I believe patch 7 breaks linux-next:

Sorry for that,

>
> Error: Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.example.dts:35.37-38
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.example.dt.yaml]
> Error 1
>
> Usually that's due to a missing include.

Indeed include are missing.

I will send a patch ASAP with a fixes tag.

Thanks for the report,
Clément

>
> Rob

[Clément Péron]

Hi Uwe, Thierry,

On Sun, 24 Nov 2019 at 18:29, Clément Péron <peron...@gmail.com> wrote:
>
> Hi,
>
> This is a rework of Jernej's previous work[1] taking account all the
> previous remarks.

Is this series ok for you?
FYI the device-tree bindings is merged in sunxi-next.

Thanks,
Clement

[Thierry Reding]

Applied, thanks.

Thierry