[GSoc 2018] [Student Introduction] Plugin for Electronic Design Automation tools

[udara de silva]

Hi everyone,

My name is Udara De Silva and I am a Ph.D student from University of Akron. I got familiar with Jenkins while working on my project https://chiphackers.com/ I am really looking forward to work on a Jenkins project for this year GSOC. In particular, I am interested in extending Jenkins capabilities in Electronic Design Automation and Verification.

My familiar programming languages are JAVA, C++, Python and Matlab. Related to the project, I am familiar with Verilog and VHDL. I have also good experience in EDA tools like Design Compiler, PrimTime, SpyGlass, VCS and Model Sim. I have worked as an R&D Engineer at Synopsys before starting my Ph.D. I have participated in GSOC 2015 where I have completed a project mentored by MyHDL open source EDA module for Python. All my project results can be found on my blog http://design4hardware.blogspot.com/

Below are couple of my online profiles:
Linked In : https://www.linkedin.com/in/udara28/
GitHub    : https://github.com/udara28


About the project: Continuous integration in electronic design (specially in IP) is a real challenge. Jenkins strengths in Software CI can be used to address this challenge. An EDA plugin will be able to post results on unit tests, coverage (support from simulators need to be studied) and publish health status of IPs to public.

Best Regards,
Udara De Silva

[Oleg Nenashev]

Hi,

Thanks again for the interest. Just to provide some context to this thread, Udara has reached out to me and Martin 2 weeks ago. Since EDA tools are not the area of interest for the most of Jenkins devs, we decided to keep this thread in private for a while until we have a rough scope defined. Currently we have a private thread discussing what would be the project scope (mostly - tools, for which we want to create plugins). And this thread is pretty long by now :)

I hope we will come back to this mailing list soon. If somebody wants to join the preliminary discussion, just respond here.

Best regards,
Oleg

[Carlos Alberto Ruiz Naranjo]

Hello,

I could help by contributing ideas. I use the continuous integration tool with FPGA (code coverage, automatic tests ...) I use GHDL.

Best regards.