Plugin(s) for FPGA / Verilog development

[Derrick Gibelyou]

Are there any plugins for FPGA development that I can contribute to?

I have been using and abusing a few software centric plugins, and am finally ready to put in some effort to get something better. I have used the Warning plugin with custom regex to create parser for the tools we use (Vivado, Modelsim, Quartus).  I have also abused the PMD plugin to display long paths (too may LUTs between Flops), but that gets confusing unless you know how I mapped 'packages' to 'source clock' and line number to number of LUTs.  I have used the plots plugin to try to plot utilization, with mediocre results.

My plan for creating an FPGA plugin would be to take several existing plugins and extend them to be more applicable to FPGA development.  First I would implement my custom regex in Java code by extending the Warning Plugin.  Then I will extend the Memory Map plugin to work for FPGA resources.  Eventually I would like to create intuitive reports for hierarchical utilization (By extending SLOCCount?) and warn about long paths (Maybe by extending a cyclomatic complexity plugin?)

Are there any good starting points, or should I plow ahead and make my own plugin?

[Oleg Nenashev]

Hi Derrick,

It would be great to see that in open-source.
I have previously implemented plugins for dozens of EDA tools at my previous jobs, but I was unable to get approvals to publish them.

• My approach in OSS would be to create mini-plugins for each tool separately so they get independent release cycles.
• Many existing plugins (like Warnings) have extension points so that they can be used in external plugins. New extension points can be added on-demand.
• Improvements to existing plugins (like hierarchical utilization) would be really useful if they are implemented in a generic way
  

FYI we also have a GSoC project idea about EDA tools: https://jenkins.io/projects/gsoc/gsoc2018-project-ideas/#integration-plugin-s-for-electronic-design-automation-tools.

Hopefully it helps,
Oleg

четверг, 1 февраля 2018 г., 3:00:11 UTC+1 пользователь Derrick Gibelyou написал:

[Ullrich Hafner]

I think it makes sense to group all things together in a new plugin (or multiple). Otherwise the different results from the different plug-ins are not visible as a single result. You don’t need to extend from an existing one,

most plugins provide extension points. E.g., the warnings plugin provides an extension point for parsers, so you just need to add one class to get the functionality. 

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[martinda]

Hi Derrick,

I have used the plot plugin and the ACL report plugin (aka summary display plugin), but I have found them difficult to work with. In terms of log parsing (regex), I have thought of creating custom filter for logstash, run logstash from the command line, and get Jenkins to read the results, rather than having Jenkins run the log parsers. This way the log parsers are usable standalone and users get the same reports with and without Jenkins. But I never got to the try my idea.

There are many toolchains in chip development (FPGA or ASIC). Each toolchain produces different types of reports. Like Oleg said, I would create a plugin for each toolchain or even each EDA tool. There could be some common underlying library code, but I would still keep the plugins independent. FPGA device utilization reports in Jenkins is an excellent idea.

As a starting point, I also suggest the GSoC proposal (see the link by Oleg).

Martin

[Derrick Gibelyou]

Thanks,

If I could go  back in time, I think I could have pulled this off as a masters project.  Sigh.

I am hoping that once there is something out there that is open source then it will be easier for people like yourself to get approval for contributing small patches.  It would be even cooler if the Tools vendors decided to contribute.

I think I will start with just the Xilinx Vivado Utilization based on the Memory Map plugin, and then wait to see what comes out of the GSoC.  That could be really exciting.

[Oleg Nenashev]

Just in case, you are welcome to join this GSoC project as a mentor.

P.S: Vivado would be cool

BR, Oleg


суббота, 3 февраля 2018 г., 21:02:04 UTC+1 пользователь Derrick Gibelyou написал: