[PATCH 0/5] Initial support for j721-evm board

[Nikhil Devshatwar]

This series adds support for the Texas Instrument's j721e-evm board.
The J721E SoC belongs to the K3 Multicore SoC architecture platform
for automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.


Lokesh Vutla (1):
ci, Documentation: Add TI's K3 specific configs

Nikhil Devshatwar (4):
configs: arm64: Add support for k3-j721-evm board
configs: arm64: Add gic and uart demos for j721-evm board
configs: arm64: Add Linux demo for j721-evm board
inmates: uart-8250: Add MDR quirk for enabling UART

ci/jailhouse-config-k3.h | 2 +
configs/arm64/dts/inmate-k3-j721e-evm.dts | 180 +++++++++++++++
configs/arm64/k3-j721e-evm-gic-demo.c | 72 ++++++
configs/arm64/k3-j721e-evm-linux-demo.c | 163 ++++++++++++++
configs/arm64/k3-j721e-evm-uart-demo.c | 72 ++++++
configs/arm64/k3-j721e-evm.c | 254 ++++++++++++++++++++++
inmates/lib/uart-8250.c | 4 +
7 files changed, 747 insertions(+)
create mode 100644 ci/jailhouse-config-k3.h
create mode 100644 configs/arm64/dts/inmate-k3-j721e-evm.dts
create mode 100644 configs/arm64/k3-j721e-evm-gic-demo.c
create mode 100644 configs/arm64/k3-j721e-evm-linux-demo.c
create mode 100644 configs/arm64/k3-j721e-evm-uart-demo.c
create mode 100644 configs/arm64/k3-j721e-evm.c

--
2.17.1

[Nikhil Devshatwar]

From: Lokesh Vutla <lokes...@ti.com>

Before building jailhouse for TI's K3 platforms,
ci/jailhouse-config-k3.h needs to be copied to
include/jailhouse/config.h

Signed-off-by: Lokesh Vutla <lokes...@ti.com>
---
ci/jailhouse-config-k3.h | 2 ++
1 file changed, 2 insertions(+)
create mode 100644 ci/jailhouse-config-k3.h

diff --git a/ci/jailhouse-config-k3.h b/ci/jailhouse-config-k3.h
new file mode 100644
index 00000000..65e02f08
--- /dev/null
+++ b/ci/jailhouse-config-k3.h
@@ -0,0 +1,2 @@
+#define CONFIG_TRACE_ERROR 1
+#define CONFIG_TI_16550_MDR_QUIRK 1
--
2.17.1

[Nikhil Devshatwar]

Add the linux demo cell config for j721e-evm board.
Also add the required device tree for booting Linux kernel
in the inmate cell.

This cell config acts as a reference for partitioning
devices across the 2 Linux cells.
This will be updated as support for more devices get added.

Signed-off-by: Nikhil Devshatwar <nikh...@ti.com>

Signed-off-by: Lokesh Vutla <lokes...@ti.com>
---

configs/arm64/dts/inmate-k3-j721e-evm.dts | 180 ++++++++++++++++++++++
configs/arm64/k3-j721e-evm-linux-demo.c | 163 ++++++++++++++++++++
2 files changed, 343 insertions(+)
create mode 100644 configs/arm64/dts/inmate-k3-j721e-evm.dts
create mode 100644 configs/arm64/k3-j721e-evm-linux-demo.c

diff --git a/configs/arm64/dts/inmate-k3-j721e-evm.dts b/configs/arm64/dts/inmate-k3-j721e-evm.dts
new file mode 100644
index 00000000..4701889f
--- /dev/null
+++ b/configs/arm64/dts/inmate-k3-j721e-evm.dts
@@ -0,0 +1,180 @@
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "Texas Instruments J721E Inmate Model";
+ compatible = "ti,j721e-evm", "ti,j721e";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial1 = &main_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@d0000000 {
+ device_type = "memory";
+ reg = <0x0 0xd0000000 0x0 0x1fff0000>;
+ };
+
+ hypervisor {
+ compatible = "jailhouse,cell";
+ };
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@1 {
+ compatible = "arm,cortex-a72","arm,armv8";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+ };
+
+ timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ pmu: pmu {
+ compatible = "arm,armv8-pmuv3";
+ /* Recommendation from GIC500 TRM Table A.3 */
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+
+ pci@76000000 {
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map =
+ <0 0 0 1 &gic 0 0 GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
+ <0 0 0 2 &gic 0 0 GIC_SPI 164 IRQ_TYPE_EDGE_RISING>,
+ <0 0 0 3 &gic 0 0 GIC_SPI 165 IRQ_TYPE_EDGE_RISING>,
+ <0 0 0 4 &gic 0 0 GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
+ reg = <0x0 0x76000000 0x0 0x100000>;
+ ranges =
+ <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
+ };
+
+ soc0: soc0 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@1800000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ /*
+ * NOTE: we are NOT gicv2 backward compat, so no GICC,
+ * GICH or GICV
+ */
+ reg = <0x0 0x01800000 0x0 0x10000>, /* GICD */
+ <0x0 0x01900000 0x0 0x40000>; /* GICR */
+ };
+ dmsc: dmsc@44083000 {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <13>;
+
+ mbox-names = "rx", "tx";
+
+ mboxes= <&secure_proxy_main 16>,
+ <&secure_proxy_main 18>;
+
+ reg-names = "debug_messages";
+ reg = <0x00 0x44083000 0x0 0x1000>;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ };
+
+ k3_clks: clocks {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ ti,scan-clocks-from-dt;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
+
+ main_uart1: serial@2810000 {
+ compatible = "ti,am654-uart";
+ reg = <0x00 0x02810000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 278 0>;
+ clocks = <&k3_clks 278 0>;
+ clock-names = "fclk";
+ };
+
+ main_sdhci0: sdhci@4f80000 {
+ compatible = "ti,j721e-sdhci-8bit";
+ reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 91 0>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
+ assigned-clocks = <&k3_clks 91 1>;
+ assigned-clock-parents = <&k3_clks 91 2>;
+ bus-width = <8>;
+ ti,otap-del-sel = <0x2>;
+ ti,trm-icp = <0x8>;
+ dma-coherent;
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ };
+
+
+ main_navss_intr: interrupt-controller1 {
+ compatible = "ti,sci-intr";
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <3>;
+ ti,sci = <&dmsc>;
+ ti,sci-dst-id = <14>;
+ ti,sci-rm-range-girq = <4>;
+ };
+
+ secure_proxy_main: mailbox@32c00000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x32c00000 0x00 0x100000>,
+ <0x00 0x32400000 0x00 0x100000>,
+ <0x00 0x32800000 0x00 0x100000>;
+ interrupt-names = "rx_016";
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+};
diff --git a/configs/arm64/k3-j721e-evm-linux-demo.c b/configs/arm64/k3-j721e-evm-linux-demo.c
new file mode 100644
index 00000000..d0eaacc3
--- /dev/null
+++ b/configs/arm64/k3-j721e-evm-linux-demo.c
@@ -0,0 +1,163 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for Linux inmate on J721E based platforms
+ * 1 CPUs, 512MB RAM, 1 serial port
+ *
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Authors:
+ * Lokesh Vutla <lokes...@ti.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+#ifndef CONFIG_INMATE_BASE
+#define CONFIG_INMATE_BASE 0x0000000
+#endif
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[10];
+ struct jailhouse_irqchip irqchips[2];
+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "j721e-evm-linux-demo",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .pio_bitmap_size = 0,
+ .cpu_reset_address = 0x0,
+ .vpci_irq_base = 195 - 32,
+ .console = {
+ .address = 0x40a00000,
+ .divider = 0x1b,
+ .type = JAILHOUSE_CON_TYPE_8250,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },
+ },
+
+ .cpus = {
+ 0x2,
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory region for 00:00.0 */ {
+ .phys_start = 0xcfb00000,
+ .virt_start = 0xcfb00000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* Main.uart1 */ {
+ .phys_start = 0x02810000,
+ .virt_start = 0x02810000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* sdhci0 */ {
+ .phys_start = 0x4f80000,
+ .virt_start = 0x4f80000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* sdhci0 */ {
+ .phys_start = 0x4f88000,
+ .virt_start = 0x4f88000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* main sproxy target_data host_id=A72_3 */ {
+ .phys_start = 0x3240f000,
+ .virt_start = 0x3240f000,
+ .size = 0x05000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* main sproxy rt host_id=A72_3 */ {
+ .phys_start = 0x3280f000,
+ .virt_start = 0x3280f000,
+ .size = 0x05000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* main sproxy scfg host_id=A72_3 */ {
+ .phys_start = 0x32c0f000,
+ .virt_start = 0x32c0f000,
+ .size = 0x05000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* linux-loader space */ {
+ .phys_start = 0xefff0000,
+ .virt_start = 0x0,
+ .size = 0x10000, /* 64KB */
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA |
+ JAILHOUSE_MEM_LOADABLE,
+ },
+ /* RAM load */ {
+ .phys_start = 0xd0000000,
+ .virt_start = 0xd0000000,
+ .size = 0x1fff0000, /* (512MB - 64KB) */
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA |
+ JAILHOUSE_MEM_LOADABLE,
+ },
+ /* communication region */ {
+ .virt_start = 0x80000000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ },
+
+ .irqchips = {
+ /*
+ * offset = (SPI_NR + 32 - base) / 32
+ * bit = (SPI_NR + 32 - base) % 32
+ */
+ {
+ .address = 0x01800000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 0x8, 0x80, 0x0, 0,
+ },
+ },
+ {
+ .address = 0x01800000,
+ .pin_base = 160,
+ .pin_bitmap = {
+ 0x0, 0x8, 0x2, 0,
+ },
+ },
+ },
+
+ .pci_devices = {
+ /* 00:00.0 */ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .bdf = 0x00,
+ .bar_mask = {
+ 0xffffff00, 0xffffffff, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000,
+ },
+ .shmem_region = 0,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
+ },
+ },
+};
--
2.17.1

[Nikhil Devshatwar]

k3-j721e-evm is the new evaluation module from Texas Instruments
which has the j721e SoC. (aka DRA829) It has a dual core
ARM Cortex-A72 CPU cores, 4GiB of RAM, 2x Display ports,
6x UART ports, 5x ethernet ports, SD and eMMC interfaces for
storage and many other connectivity, graphics, multimedia and
other accelerator devices.

J721E TRM: http://www.ti.com/lit/ug/spruil1/spruil1.pdf

Add support for the jailhouse root cell config for this board.

Signed-off-by: Nikhil Devshatwar <nikh...@ti.com>
Signed-off-by: Lokesh Vutla <lokes...@ti.com>
---

configs/arm64/k3-j721e-evm.c | 254 +++++++++++++++++++++++++++++++++++
1 file changed, 254 insertions(+)
create mode 100644 configs/arm64/k3-j721e-evm.c

diff --git a/configs/arm64/k3-j721e-evm.c b/configs/arm64/k3-j721e-evm.c
new file mode 100644
index 00000000..2ab2c3ce
--- /dev/null
+++ b/configs/arm64/k3-j721e-evm.c
@@ -0,0 +1,254 @@

+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *

+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *

+ * Configuration for K3 based J721E-EVM

+ *
+ * Authors:

+ * Nikhil Devshatwar <nikh...@ti.com>

+ * Lokesh Vutla <lokes...@ti.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+

+struct {
+ struct jailhouse_system header;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[18];
+ struct jailhouse_irqchip irqchips[6];

+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {

+ .header = {
+ .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
+ .hypervisor_memory = {
+ .phys_start = 0xcfc00000,
+ .size = 0x400000,
+ },
+ .debug_console = {
+ .address = 0x02800000,
+ .size = 0x1000,

+ .type = JAILHOUSE_CON_TYPE_8250,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },

+ .platform_info = {
+ .pci_mmconfig_base = 0x76000000,
+ .pci_mmconfig_end_bus = 0,
+ .pci_is_virtual = 1,
+ .pci_domain = 1,
+ .arm = {
+ .gic_version = 3,
+ .gicd_base = 0x01800000,
+ .gicr_base = 0x01900000,
+ .maintenance_irq = 25,
+ },
+ },
+ .root_cell = {
+ .name = "k3-j721e-evm",

+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),

+ .vpci_irq_base = 191 - 32,

+ },
+ },
+
+ .cpus = {

+ 0x3,

+ },
+
+ .mem_regions = {

+ /* ctrl mmr */ {
+ .phys_start = 0x00100000,
+ .virt_start = 0x00100000,
+ .size = 0x00020000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },

+ /* GPIO */ {
+ .phys_start = 0x00600000,
+ .virt_start = 0x00600000,
+ .size = 0x00002000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },

+ /* IVSHMEM shared memory region for 00:00.0 */ {
+ .phys_start = 0xcfb00000,
+ .virt_start = 0xcfb00000,
+ .size = 0x100000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* serdes */ {
+ .phys_start = 0x00900000,
+ .virt_start = 0x00900000,
+ .size = 0x00012000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },

+ /* Most peripherals */ {
+ .phys_start = 0x01000000,
+ .virt_start = 0x01000000,
+ .size = 0x0af03000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },

+ /* MAIN NAVSS */ {
+ .phys_start = 0x30800000,
+ .virt_start = 0x30800000,
+ .size = 0x0bc00000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },

+ /* PCIe Core */ {
+ .phys_start = 0x0d000000,
+ .virt_start = 0x0d000000,
+ .size = 0x01000000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },

+ /* PCIe DAT */ {
+ .phys_start = 0x10000000,
+ .virt_start = 0x10000000,
+ .size = 0x10000000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },

+ /* GPU */ {
+ .phys_start = 0x4e20000000,
+ .virt_start = 0x4e20000000,
+ .size = 0x80000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+

+ },
+ /* MCUSS */ {
+ .phys_start = 0x28380000,
+ .virt_start = 0x28380000,
+ .size = 0x03880000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },

+ /* MCUSS */ {
+ .phys_start = 0x40200000,
+ .virt_start = 0x40200000,
+ .size = 0x00901000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },

+ /* MCUSS */ {
+ .phys_start = 0x42040000,
+ .virt_start = 0x42040000,
+ .size = 0x03ac3000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },

+ /* MCUSS */ {
+ .phys_start = 0x45100000,
+ .virt_start = 0x45100000,
+ .size = 0x00c24000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },

+ /* MCUSS */ {
+ .phys_start = 0x46000000,
+ .virt_start = 0x46000000,
+ .size = 0x00200000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },

+ /* MCUSS */ {
+ .phys_start = 0x47000000,
+ .virt_start = 0x47000000,
+ .size = 0x00069000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },

+ /* RAM */ {
+ .phys_start = 0x80000000,
+ .virt_start = 0x80000000,
+ .size = 0x4fb00000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |

+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* RAM. Reserved for inmates */ {

+ .phys_start = 0xd0000000,
+ .virt_start = 0xd0000000,

+ .size = 0x20000000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |

+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* RAM. */ {
+ .phys_start = 0xf0000000,
+ .virt_start = 0xf0000000,
+ .size = 0x10000000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |

+ JAILHOUSE_MEM_EXECUTE,
+ },
+ },
+ .irqchips = {

+ {
+ .address = 0x01800000,
+ .pin_base = 32,
+ .pin_bitmap = {

+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,

+ },
+ },
+ {
+ .address = 0x01800000,
+ .pin_base = 160,
+ .pin_bitmap = {

+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,

+ },
+ },
+ {
+ .address = 0x01800000,

+ .pin_base = 288,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,

+ },
+ },
+ {
+ .address = 0x01800000,

+ .pin_base = 416,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,

+ },
+ },
+ {
+ .address = 0x01800000,

+ .pin_base = 544,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,

+ },
+ },
+ {
+ .address = 0x01800000,

+ .pin_base = 800,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,

+ },
+ },
+ },
+
+ .pci_devices = {

+ /* 0001:00:00.0 */ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 1,

+ .bdf = 0x00,
+ .bar_mask = {
+ 0xffffff00, 0xffffffff, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000,
+ },

+ .shmem_region = 2,

[Nikhil Devshatwar]

UART is disabled by default on TI platforms and must be enabled
on some platforms via the MDR register.
Do this as part of uart_init for 8250 driver

Signed-off-by: Nikhil Devshatwar <nikh...@ti.com>
Signed-off-by: Lokesh Vutla <lokes...@ti.com>
---

inmates/lib/uart-8250.c | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/inmates/lib/uart-8250.c b/inmates/lib/uart-8250.c
index fb7940d2..42b0979c 100644
--- a/inmates/lib/uart-8250.c
+++ b/inmates/lib/uart-8250.c
@@ -49,6 +49,7 @@
#define UART_LCR_DLAB 0x80
#define UART_LSR 0x5
#define UART_LSR_THRE 0x20
+#define UART_MDR1 0x8

static void reg_out_mmio32(struct uart_chip *chip, unsigned int reg, u32 value)
{
@@ -67,6 +68,9 @@ static void uart_8250_init(struct uart_chip *chip)
chip->reg_out(chip, UART_DLL, chip->divider);
chip->reg_out(chip, UART_DLM, 0);
chip->reg_out(chip, UART_LCR, UART_LCR_8N1);
+#ifdef CONFIG_TI_16550_MDR_QUIRK
+ chip->reg_out(chip, UART_MDR1, 0);
+#endif
}
}

--
2.17.1

[Nikhil Devshatwar]

Add GIC and UART demo cell configs for j721e-evm board.
This can be used to run the standard jaiilhouse baremetal
inmate demos like gic-demo and uart-demo.

Signed-off-by: Nikhil Devshatwar <nikh...@ti.com>
Signed-off-by: Lokesh Vutla <lokes...@ti.com>
---

configs/arm64/k3-j721e-evm-gic-demo.c | 72 ++++++++++++++++++++++++++
configs/arm64/k3-j721e-evm-uart-demo.c | 72 ++++++++++++++++++++++++++
2 files changed, 144 insertions(+)
create mode 100644 configs/arm64/k3-j721e-evm-gic-demo.c
create mode 100644 configs/arm64/k3-j721e-evm-uart-demo.c

diff --git a/configs/arm64/k3-j721e-evm-gic-demo.c b/configs/arm64/k3-j721e-evm-gic-demo.c
new file mode 100644
index 00000000..f92cd880
--- /dev/null
+++ b/configs/arm64/k3-j721e-evm-gic-demo.c
@@ -0,0 +1,72 @@

+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *

+ * Configuration for gic-demo inmate on K3 based platforms.
+ * 1CPU, 64K RAM, 1 serial port.

+ *
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *

+ * Authors:
+ * Nikhil Devshatwar <nikh...@ti.com>
+ * Lokesh Vutla <lokes...@ti.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {

+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[3];
+} __attribute__((packed)) config = {

+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,

+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "gic-demo",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,

+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),

+ .num_irqchips = 0,
+ .pio_bitmap_size = 0,
+ .num_pci_devices = 0,
+
+ .console = {
+ .address = 0x02810000,
+ .divider = 0x1b,

+ .type = JAILHOUSE_CON_TYPE_8250,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },

+ },
+
+ .cpus = {

+ 0x2,

+ },
+
+ .mem_regions = {

+ /* UART 3 */ {

+ .phys_start = 0x02810000,
+ .virt_start = 0x02810000,

+ .size = 0x10000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* RAM */ {

+ .phys_start = 0xd0000000,
+ .virt_start = 0,
+ .size = 0x00010000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |

+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,

+ },
+ /* communication region */ {

+ .virt_start = 0x80000000,
+ .size = 0x00001000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |

+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ }
+};
diff --git a/configs/arm64/k3-j721e-evm-uart-demo.c b/configs/arm64/k3-j721e-evm-uart-demo.c
new file mode 100644
index 00000000..ea0cba42
--- /dev/null
+++ b/configs/arm64/k3-j721e-evm-uart-demo.c
@@ -0,0 +1,72 @@

+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *

+ * Configuration for uart-demo inmate on K3 based platforms:
+ * 1 CPU, 64K RAM, serial port 3

+ *
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *

+ * Authors:
+ * Nikhil Devshatwar <nikh...@ti.com>
+ * Lokesh Vutla <lokes...@ti.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {

+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[3];
+} __attribute__((packed)) config = {

+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,

+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "uart-demo",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,

+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),

+ .num_irqchips = 0,
+ .pio_bitmap_size = 0,
+ .num_pci_devices = 0,
+
+ .console = {
+ .address = 0x02810000,
+ .divider = 0x1b,

+ .type = JAILHOUSE_CON_TYPE_8250,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },

+ },
+
+ .cpus = {

+ 0x2,

+ },
+
+ .mem_regions = {

+ /* UART 3 */ {

+ .phys_start = 0x02810000,
+ .virt_start = 0x02810000,

+ .size = 0x10000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* RAM */ {

+ .phys_start = 0xd0000000,
+ .virt_start = 0,
+ .size = 0x00010000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |

+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,

+ },
+ /* communication region */ {

+ .virt_start = 0x80000000,
+ .size = 0x00001000,

+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |

+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ }
+};
--
2.17.1

[Ralf Ramsauer]

Hi Lokesh,

I think it's better to encode this in struct uart's flags. We still have
some bits free there.

It's better to not reintroduce compile time switches, it took a while to
get rid of (most of) them.

Ralf

> }
> }
>
>

[Jan Kiszka]

We only track in ci/ what we enabled for ci. In any case, when following Ralf's
proposal for patch 4, this should be obsolete.

Jan

--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux

[Nikhil Devshatwar]

On 24/05/19 7:37 AM, Jan Kiszka wrote:
> On 23.05.19 23:16, 'Nikhil Devshatwar' via Jailhouse wrote:
>> From: Lokesh Vutla <lokes...@ti.com>
>>
>> Before building jailhouse for TI's K3 platforms,
>> ci/jailhouse-config-k3.h needs to be copied to
>> include/jailhouse/config.h
>>
>> Signed-off-by: Lokesh Vutla <lokes...@ti.com>
>> ---
>>   ci/jailhouse-config-k3.h | 2 ++
>>   1 file changed, 2 insertions(+)
>>   create mode 100644 ci/jailhouse-config-k3.h
>>
>> diff --git a/ci/jailhouse-config-k3.h b/ci/jailhouse-config-k3.h
>> new file mode 100644
>> index 00000000..65e02f08
>> --- /dev/null
>> +++ b/ci/jailhouse-config-k3.h
>> @@ -0,0 +1,2 @@
>> +#define CONFIG_TRACE_ERROR        1
>> +#define CONFIG_TI_16550_MDR_QUIRK    1
>>
>
> We only track in ci/ what we enabled for ci. In any case, when

> following Ralf's proposal for patch 4, this should be obsolete. '

Alright, I will repost the series taking into consideration the UART
flag and drop this patch.

Regards,

Nikhil D



>
> Jan
>

[Nikhil Devshatwar]

I looked up in the source.
The flags are only for the console.
Here we need this to be written from the inmate, which doesn't know about the console flags.
Which struct uart are you referring to?

Nikhil D

[Ralf Ramsauer]

if (comm_region->console.flags & JAILHOUSE_CON_MDS_QUIRK)

>>> +        chip->reg_out(chip, UART_MDR1, 0);
>>> +#endif
>>
>> I think it's better to encode this in struct uart's flags. We still have
>> some bits free there.

s/struct uart/struct jailhouse_console/

>
> I looked up in the source.
> The flags are only for the console.
> Here we need this to be written from the inmate, which doesn't know
> about the console flags.

We do pass the flags to the inmate via the communication region. See
hypervisor/control.c:657. Just pick a reserved bit.

Ralf

[Nikhil Devshatwar]

Oh okay.
Using console flag for setting up uart didn't sound right to me.
Here the inmate has a dedicated uart instance, not shared with the root cell.

If that's the preferred option, I'll do that.
Of course both uarts have the same behavior.

Nikhil D

[Ralf Ramsauer]

But that's okay. The inmate also has a dedicated struct
jailhouse_console that is not shared with the root cell config. Am I
missing something?

Ralf