Need help with versa5 registers

[Ian A]

Hi

I am  modifying hermeslite.py a bit so i can generate a 116mhz clock on CL2 for a 2m transverter. I cant quite get my head around the versa registers, so the  divider will be 11.255172414 what will that make the 6 registers??

Also can the T/R relay be enabled / disabled from hermeslite.py

Thanks

Ian VK2AMA

[Ian A]

Ok have it now, after sleeping on it I realized I needed to do some bit shifting.

[Josh Logan]

What parameters did you use?

73, Josh

KD7HGL

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[Steve Haynal]

Hi Ian,

Your divisor looks correct given the default 1305.6 MHz VCO. Refer to the programming guide:

https://www.renesas.com/us/en/document/mau/versaclock-5-family-register-descriptions-and-programming-guide

for how to set the fractional portion. 

(2**24) * .255172414 = 0x4152fa

This is a 24-bit number, but they allocate 30 bits for the fractional portion. I don't know why. From the programming guide:

From Eq.10,(224 * 0.15643939) = 2624617.502. → Odx_offset [29:0] = 280C69

I interpret this as the higher order bits [29:24] being all zero for positive numbers, or all one for sign-extended negative numbers. Also not sure when you'd want a negative number here.

73,

Steve

kf7o

[Alan Hopper]

Hi Ian,

I'm interested to see your settings, adding this to spark is on my ever growing list.

73 Alan M0NNB

[Ian A]

Thanks everyone for the reply's.

This is what I came up with after modifying Steve's 'enable_cl2_61p44()' routine but very much a work in progress.

 It looked right to me, but after seeing your post Steve maybe not so much!

 I haven't had a chance to test it as i get the " Retrying Send" errors from hermeslite.py.

 Presumably  port 1025 is not enabled on the HL2, How is that accomplished? The gateware is 72.8

Alan just to add to your list;-) For transverse use It would be great one day to have the PA enable setting and TR disable setting saved with the profile

and even better the transverter off-set saved for each receiver but can't complain, Spark works great as it is.

 def enable_cl2_116(self):
    """Enable CL2 output at 116 MHZ"""
    self.write_versa5(0x62,0x3b) ## Clock2 CMOS1 output, 3.3V
    self.write_versa5(0x2c,0x00) ## Disable aux output on clock 1
    self.write_versa5(0x31,0x81) ## Use divider for clock2

    self.write_versa5(0x3d,0x00)
    self.write_versa5(0x3e,0xb0)
   
    self.write_versa5(0x32,0x01) ## [29:22]
    self.write_versa5(0x33,0x05) ## [21:14]
    self.write_versa5(0x34,0x4b) ## [13:6]
    self.write_versa5(0x35,0xe8) ## [5:0] and disable ss 
    self.write_versa5(0x63,0x01) ## Enable clock2

Cheers and 73

Ian VK2AMA

[Ian A]

OK now after the 3rd attempt  the firewall is properly configured for port 1025 and am getting 116.0015mHz on CL2 with the above register values.

The frequency counter is not to be trusted so the accuracy is probably much better than that.

73 

Ian VK2AMA

[Matthew]

I would be interested to hear a little more about this. Presumably you are feeding a diode ring mixer with the 116 MHz signal? What does your circuit look like between the SMA connector and the mixer in terms of buffering/filtering/amplification?

There is a good point of reference with Hamish's design but it would be interesting to hear more about your approach.

73 Matthew M5EVT.

[Ian A]

Matthew, I have one of the Ukrainian transverters  with the ADE-1 mixer, they have their known issues but it is  starting point, ill probably eventually build something better.

Atm the CL2 is feeding the ADE1 through 33pf and 470ohms and is working ok for a first attempt, the square wave into the DBM doesn't appear to be producing any more crud than the original Xtl oscillator but that needs a further look.

Steve, Thanks the Renesas programing guide got me got me started in the right direction but some there  is still clear as mud, anyway  the 2 bit left shift on 0x4152fa produced  the desired result.

73

Ian VK2AMA

[James Ahlstrom]

Hello Ian,

Quisk has code to set the CL2 output frequency. See hermes/quisk_hardware.py and search for "Versa". The code is in Python and is easy to read.

Jim

N2ADR

[Ian A]

Thanks Jim,

What is the best way to call that function run each time Quisk connects to the HL2

Ian VK2AMA

[James Ahlstrom]

Hello Ian,

The best way to customize Quisk is to write your own hardware file in Python, and set the name in the Config/radio/Hardware screen. You would add code to set the Versa registers in a replacement open() function so it is called when the hardware is opened.

Jim

N2ADR

[Ian A]

Thanks Jim,

OK, I'll do that.

73

Ian vk2ama