FuPy progress at PyConAU 2018 in Sydney, Australia

[Ewen McNeill]

Several FuPy developers, and several upstream MicroPython developers
were at the PyConAU 2018 conference held in Sydney, Australia a couple
of weeks ago (https://2018.pycon-au.org/ -- the videos of all talk
sessions are on YouTube).

We had three days of work on MicroPython / FuPy and the litex-buildenv
(https://github.com/timvideos/litex-buildenv; used as part of building
FuPy) -- one day before PyConAU 2018, and two more days at the PyConAU
2018 Sprints.

Some of the key progress made at PyConAU 2018 includes:

* Lots of people tried out FuPy at the Sprints

* A new HowTo was written on getting FuPy running on a Digilent Arty A7
board:

https://github.com/timvideos/litex-buildenv/wiki/HowTo-FuPy-on-a-Digilent-Arty-A7

by one of the people trying out FuPy (also now linked on the FuPy
website -- https://fupy.github.io/).

* Our MicroPython fork (https://github.com/fupy/micropython) updated to
merge in all the upstream MicroPython
(https://github.com/micropython/micropython) changes up to late August
2018. We now have MicroPython 1.9.4 (plus some patches for our port,
and development upstream since 1.9.4):

Executing booted program at 0x40000000
MicroPython v1.9.4-514-g7e26f0c-dirty on 2018-08-28; litex with lm32
>>>

* As part of this update, we've moved our port from the "litex" top
level directory into the "ports/fupy" directory, which matches the
upstream changes to move all ports into the "ports" directory.

* We also discussed the possibility of merging FuPy back into upstream
MicroPython later. Updating our port to follow upstream, and matching
the upstream directory layout were steps towards assisting a later merge
back upstream.

* Both Digilent Arty A7 and Mimas V2 platforms have been tested with the
"lm32" soft CPU.

* Progress was made on getting the "or1k" soft CPU working with FuPy:

https://github.com/fupy/micropython/issues/3

(help wanted on resolving the remaining MicroPython compile/link issues)

* A start was made on getting RISC V soft CPUs working (vexriscv,
picov32); this needs more work, mostly around getting compilers
packaged, and interrupt handling for MicroPython. (Help wanted :-) )

* A start was made on getting litex-buildenv and FuPy working on the
iCE40 FPGA platform (which has an open source, reverse engineered, tool
chain), particularly on the TinyFPGA BX board:

https://tinyfpga.com/bx/guide.html
https://www.crowdsupply.com/tinyfpga/tinyfpga-bx

The TinyFPGA BX support development has continued in the couple of weeks
since the PyConAU 2018 sprints and is making good progress, but not yet
fully booting. If you want to follow this progress, watch #timvideos on
Freenode (eg, in the IRC logs -- https://logs.timvideos.us/%23timvideos/).

Ewen