Benchsim: Simulación sencilla para Icestudio / Simple Simulation for Icestudio

[lmcapacho]

Hola 

Quería compartir una herramienta que desarrollé para facilitar la simulación de proyectos en Icestudio usando los testbench generados automáticamente.

Se llama benchsim: https://github.com/lmcapacho/benchsim

Con tener instalados iverilog y gtkwave, y usando main.v junto con el testbench que genera Icestudio, se puede correr la simulación fácilmente y modificar el testbench si es necesario.

También funciona con archivos Verilog y testbench que no hayan sido generados en Icestudio.

Cualquier feedback es bienvenido

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Hi

I’d like to share a tool I developed to simplify the simulation of Icestudio projects using the automatically generated testbenches.

It’s called benchsim: https://github.com/lmcapacho/benchsim

With iverilog and gtkwave installed, and using main.v together with the testbench generated by Icestudio, you can easily run simulations and modify the testbench if needed.

It also works with Verilog files and testbenches that were not generated by Icestudio.

Any feedback is welcome

[Carlos Venegas]

Lo acabo de probar y tiene muy buena pinta , ¡Enhorabuena! es una herramienta que puede facilitar mucho el uso de los testbenches para quien no los tenga en su flujo, habrá que meterle a icestudio un acceso directo!

Gracias por compartirlo tienes entre manos el germen de algo que puede ser prometedor, andaré pendiente de los avances.

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[lmcapacho]

Hola Carlos, 

Muchas gracias por los comentarios, siempre pendiente de todos los mensajes. 

Como dices puede ser el inicio de una propuesta para Icestudio o con algunos cambios puede ser parte de Apio y Icestudio. 

Saludos, 

[Jo mo]

Hola luis miguel,

I am testing your tool ant it is very easy to install and run.
The only think, is a am new to this test bench usages and have some trouble understanding how to deal with test bench files.

Even the simple led blink module that i am testing gives me troubles.

For now what i understand is that the testbench files generated by icestudio need to be modified a lot to make simulation work! eg the clock signal is not fully predefined in the -tb file.

As we need to edit quite a lot this tb files, will it be interesting to have some undo/redo, save "version of -tb" file functions in you benchSim tool (maybe under another extension, as the tool only want one testbench file in the folder) ?

i keep testing/learning ...

Any way thanks a lot for this great tool that we should insert in our icestudio kebab ;-)

have a great Sunday guys!

[Jo mo]

Also, we have to see how to deal with the fact that a new icestudio build, of that same design overwrite the -tb file! so we can loose our modifications on the testbench file!...

[Carlos Venegas]

The simulation aspect is very important, and it's something that IceStudio has never really emphasized. But for me, for example, for the more complex things I do, it's essential to be able to work first by creating simulations, even if it's just of parts of the design. Everything will come in time, but Luis Miguel's tool is certainly a good start.

Para ver este debate, visita https://groups.google.com/d/msgid/fpga-wars-explorando-el-lado-libre/acfdfb28-34be-4b05-b3b6-037b7e46f595n%40googlegroups.com.

[lmcapacho]

Hi Joaquin,

Thanks a lot for testing the tool and for your feedback, I really appreciate it!

About the testbench: you actually don’t need to modify it too much to validate your design. In most cases, you only need to change the stimuli in this section:

// TODO: initialize the registers here
// e.g. value = 1;
// e.g. #2 value = 0;

That’s where you define the input signals for your design.

For clocked circuits, just make sure you have an input named clk (lowercase) and connect your clock to that signal. Icestudio automatically adds this to the testbench:

// Clock signal
always #0.5 clk = ~clk;

Also, designs like a simple LED blink are not the best candidates for simulation. Since the on/off timing is usually very long (many clock cycles), you would need a huge number of simulation steps, which makes the simulation slow and not very practical. For this kind of design, simulation is usually less useful unless you reduce the counter values just for testing.

And about Icestudio overwriting the -tb file when rebuilding: that’s a very good point. I’m actually working on that now, since preventing users from losing their testbench changes is definitely important.

Thanks again for the great feedback!