Uso de pines bidireccionales para manejar buses de datos de memorias externas

[beni...@gmail.com]

Buenas a todos:

Estoy añadiendo una nueva placa al ICeStudio , , la placa en concreto es la SIMRETRO
http://www.ele.uva.es/~jesus/SIMRETRO/index.html

La parte del programador ya la tengo resuelta , existia un software en linux para programarla partiendo de un bitfile, lo he pasado a windows con autodeteccion de puerto y funciona bien. 

En breve subire el pull request de esa placa 

Pero a la hora de introducir la SRAM y querer probarla me ha sugido el problema

Como se puede usar un pin de entrada y salida sin tener que usar modulos triestados o cosas raras ???
Quiero añadir las lineas del bus de datos de la SRAM.

Esto mismo pasa con las ULX3, Colorlight o ICeSugar pro o la ECP5-Evaluation Board que tienen SDRAM. 

Por que IceStudio no tiene una opcion de pin bidirecional ??? Se podria añadir esa opcion ?

Gracias y un Saludo

Fernando Mosquera

[charli va]

Hola Benito! gran trabajo! ¿tendrías un ejemplo de cómo lo hacen la ULXS3 por ejemplo? para ver como introducir esta funcionalidad que comentas que es muy interesante.

Gracias!

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[beni...@gmail.com]

Hola Charliva

Los del ULX3 ellos al menos a nivel del controlador SDRAM usan la siguiente primitiva que he sacado de este ejempo
https://github.com/daveshah1/ulx3s/blob/master/rtl/verilog/orpsoc_top.v#L456

TRELLIS_IO #(.DIR("BIDIR")) sdram_dq_buf_0 (.B(sdram_dq_pad_io[0]), .I(sdram_dq_o[0]), .O(sdram_dq_i[0]), .T(!sdram_dq_oe));

En donde la linea  sdram_dq_pad_io[0] en este caso es una linea Inout.  OJO:  creo que este ejemplo es desdram_dq_pad_io[0] que es parte de un bloque  (   inout [15:0] sdram_dq_pad_io,  ) que representa pines de la FPGA al ser un modulo TOP

Esto quiere decir que el toolchain lo admite pero.... como defino en ICeStudio que esa linea  sdram_dq_pad_io pudiera ser un pin INOUT ?

Saludos 

Fernando

[charli va]

Voy a investigar y os cuento!

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[Juan Gonzalez Gomez]

Hola,

En este cuaderno técnico está la información de los pines de Entrada/Salida, y los bloques a usar en icestudio

https://github.com/Obijuan/Cuadernos-tecnicos-FPGAs-libres/wiki/CT.3:-Pines-de-Entrada-Salida

Los ejemplos están hechos para la ice40, pero para el resto de fpgas es similar. Sólo hay que localizar el nombre del modulo de la fpga encargado de configurar el pin. Y con esa información ya se puede implementar el bloque en icestudio fácilmente

Cualquier ejemplo que se encuentre en verilog que ya lo haga para esa FPGA se puede integrar en icestudio directamente

Saludos, Obijuan

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[beni...@gmail.com]

Gracias Obijuan,

Segun veo en el ejemplo de entrad/Salida usando el mismo PIN , se usa en el caso del ICE40 esta primitiva

 

SB_IO #(

      .PIN_TYPE(6'b1010_01),

      .PULLUP(1'b0)

  ) triState (

      .PACKAGE_PIN(pin),

      .OUTPUT_ENABLE(oe),

      .D_OUT_0(dout),

      .D_IN_0(din)

  );

Creo que la misma primitiva para el ECP5 es esta

TRELLIS_IO #(

       .DIR("BIDIR")

  ) siod_out_bidir (

      .B(pin),

      .T(oe),

      .I(dout),

      .O(din)

  );

A ver si lo puedo probar

Saludos

Fernando

[beni...@gmail.com]

Ya probe los modulos para entradas bidireccionales adaptados para las placas ECP5
Funcionan perfectamente

Seria conveniente añadirlos a una Coleccion Especifica para placas ECP5 ya que son primitivas que solo funcionan en estas placas FPGA

Adjunto los dos modulos in-out_ECP5  y el in-out-right_ECP5

Saludos 

Fernando Mosquera

[Jo mo]

Ola Fernando,

Thanks a lot for those blocks,

Personally, i will prefer to stored them in the same collection as the modules for ice40  but with an _ECP5 extension (as you did for these two blocks)

And i will rename the actual inout blocks present in the collection with an extension _ice40.

so, we will have in that collection something like:

-....

-pines

     -  In-out_ICE40

     -  In-out_ECP5

     -  In-out-right_ICE40

     -  In-out-right_ECP5

-...

@Obijuan:

Can we do pull request to store our blocks in an icestudio collection?  For example: loading Fernando block in the Jedi collection (or maybe in the IceInputs collection)?

of course, prior to those pull request, the modules should be presented and discussed with you here in the forum.

Or if you just prefer that people do not modify your collections, we can create our own collection and share it with the FPGawars community!

for exemple: IceDemocrito collection, IceBenito collection,...

in this last case, is there a little/simple tutorial for the creation of a collection?

it will be nice if we find a good/easy way to start storing/sharing all those block created by democrito, Fernando(Benitos) and others,...

Thanks and have a nice week guys!

Joaquim

...

[Obijuan]

Hi!

El lunes, 6 de diciembre de 2021 a las 1:24:38 UTC+1, joa...@gmail.com escribió:

Ola Fernando,

Thanks a lot for those blocks,

Personally, i will prefer to stored them in the same collection as the modules for ice40  but with an _ECP5 extension (as you did for these two blocks)

And i will rename the actual inout blocks present in the collection with an extension _ice40.

so, we will have in that collection something like:

-....

-pines

     -  In-out_ICE40

     -  In-out_ECP5

     -  In-out-right_ICE40

     -  In-out-right_ECP5

-...

Thanks for the blocks Fernando! 

I agree with you Joaquim. Your proposal is ok for me

@Obijuan:

Can we do pull request to store our blocks in an icestudio collection?  For example: loading Fernando block in the Jedi collection (or maybe in the IceInputs collection)?

of course, prior to those pull request, the modules should be presented and discussed with you here in the forum.

You can always pull-req any block for sure! Pull request are always welcome. As the blocks are something no critical (in the sense that icestudio will not break if you add a new block) you can do the pull-reqs and later we can change names/collection or whatever according to the discussions

For the io pins my proposal is to create the iceIO collection. In there we can store the in_out_ICE40, in_out_ECP5 blocks as well as the blocks for configuring the pull-ups for the different boards (pull-up_ECP5, pull_up_ICE40)

As these modules are specific to a particular FPGA, I think it makes sense to have them all in a new collection

 

Or if you just prefer that people do not modify your collections, we can create our own collection and share it with the FPGawars community!

for exemple: IceDemocrito collection, IceBenito collection,...

in this last case, is there a little/simple tutorial for the creation of a collection?

Any pull-request to any collection belonging to FPGAwars will be accepted for sure. I prefer that people first do the pull-req and then the discussions. To avoid delays on the acceptance of the pull-requests we can give write permissions to any user who has already contributed (like Joaquim, Democrito, Fernando...)

Also, any user can create their own collection in their own repository at any moment, of course. Creating a collection is very simple. I did not have the time to document it properly in English yet, but I did it in Spanish some years ago:

https://github.com/Obijuan/digital-electronics-with-open-FPGAs-tutorial/wiki/V%C3%ADdeo-23:-Mi-primera-colecci%C3%B3n

The easiest ways is to copy the structure of a previous collections, removing the blocks (from the block folder), removing the examples (from the examples folder) and adding the new ones. Al the meta-information related to the collection is stored on the package.json file. The reference collection should be the iceK (it is the latest collection. It is already documented in english and translated into Spanish):

https://github.com/FPGAwars/iceK/wiki

it will be nice if we find a good/easy way to start storing/sharing all those block created by democrito, Fernando(Benitos) and others,...

Yes, for sure. My proposal is to first start with the iceIO collection. I can create it from scratch, with the correct structure. Then any of you can do pull-request. Some of you can have write access so that you can merge pull-req from other users

Best regards, Obijuan

[Jo mo]

Ola Obijuan,

Thanks a lot for these detailed reply, your proposals are great for me! Let us do it !

Have a good day

Joaquim

[Obijuan]

iceIO repo created!

https://github.com/FPGAwars/iceIO

I've also create a team for working on collections and invited Democrito, Fernando and Joaquim. You should have write access to the icestudio collection repos (not all yet) 

I need you to check that you have write accesss to iceIO and icePLL. Also check if you can edit their wiki pages (there is no information at the moment). I am not totally sure but should also have permission for accepting pull-request from others

I've also added a list of the current collections I am working on to the Icestudio wiki documentation.  You can see them on the side panel:

https://github.com/FPGAwars/icestudio/wiki

Only the iceK is considered stable (it has a lot of documentation, examples and it is 100% in English). The other collections are a work in progress

Best regards, Objuan

[Jo mo]

Ola Obijuan,

Thank a lot for adding me to the collection team!

i checked  my write access and it is not active (for both icePLL and iceIO). 

i got this message:

    " You’re making changes in a project you don’t have write access to. Submitting a change will write it to a new branch in your fork jojo535275/iceIO, so you can send a pull request."

have a good evening

joaquim

[Obijuan]

ok, I think I've fixed that.  Could you please try it again? I have not worked with teams before and I am not sure how to set the right permissions

Obijuan

El martes, 7 de diciembre de 2021 a las 20:48:04 UTC+1, joa...@gmail.com escribió:

Ola Obijuan,

[Jo mo]

yes, i just tried and i now have write access for the two collections!

i'm also just starting with Github team work !

thanks

Joaquim