Hi,
I got my hands on an Orangecrab-25 board with 25K-LUT ECP5. And these are my first impressions:
- Definitely, a RESET button is strongly needed, unless you are happy with unplugging an reconnecting the USB cable every time you want to upload a bitstream. (The RESET signal is at least available on the pins, so, a switch to ground can act as the missing reset button)
- The USB bootloader is slow, maybe because the SPI flash is erased and reprogrammed every time a bitstream is uploaded. The JTAG programming is still untested.
- The included DDR3 DRAM is hard to use, unless an already built controller example is provided (I'm still searching for it ;) A prebuilt example is running Linux on a RiscV with 64MB of RAM (the chip has 128MB) but its sources aren't very useful for me...
- The Analog section (multiplexer plus LVDS comparator) is going to be slow due to a long RC constant, and probably also very noisy due to the switched power regulators of the supply rails. I don't expect much from it.
And I also want to present a comparative between the ECP5 and the ICE40, both synthesizing the same design (a simpler RiscV core, plus 8KB of internal memory, plus an USB_CDC pseudo-UART):
ICE40 ECP5
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LCs: 4944 FF: 980
Comb.: 5311
RAMW: 24
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Total: 6315
BRAMs: 16 (50%) DP16K: 4 (7.2%)
max. CLK: 29MHz 37MHz (still runs at 48MHz)
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Well, the ECP5 requires more logic cells, about a 30% more than the ICE40 version, but with almost 25000 LCs we have a lot more space for designs.
In the ECP5 the internal BRAMs are 4 times the size of the ICE40 (16Kbit or 2Kbytes), totaling 112Kbytes, that's a lot more. Also, in the ECP5 the LCs can be turned into small SRAMs (listed as RAMW, or distributed RAM...)
Finally, the clock frequency is higher for the ECP5, but not much higher, only a 30% more.
Regards