New OS X Installation

[Nigel Smith]

I've been using Icestudio for a week or so and have made some good progress with my design. But now every time I open a new window, I am asked to re-install the toolchain and the drivers. And when I build and upload my design I have to go through the usual hassle of telling the Mac to ignore its security concerns for multiple files. Once I have done this, I can upload my file to my Icebreaker board and run it. Except for designs with a PLL instantiation which was previously working – I get a build error for that at the moment.

I've had a look through this forum, and although I can see some posts related to installing on a Mac, it's not clear to me what I should do to install Icestudio properly, so that I don't have to keep installing the toolchain etc.

My Mac has an M1 processor, and is running Sonoma 14.1.

I am an experienced electronics engineer (mainly analog) but not a computer hacker, and therefore any proposed solutions should be explained in fairly simple terms (preferably with an explanation of why each step is necessary). I think this is an important point, because as far as I can tell, Icestudio is targeted at beginners, and therefore a simple and robust installation is essential.

Thanks in advance for any help.

[charli va]

Hi Nigel! the installation in M1, is little tricky, i'm working in a new version more easy to install in it  think i'm having it in a couple of days as much. If you could test when this is available would be very helpful.

About the error of your PLL, could you give us an screenshot of your error? or if you could send us your design or part of it with the problem.

Your feedback about the blocks manager was very good and in next versions the behaviour takes your suggestions. 

All of your feedback about the installation is very helpful, my idea is that icestudio should be very easy to install in all of the systems and we need to improve a lot of things.

Thanks a lot!

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[Nigel Smith]

Hi!

In the meantime, I managed to get my PLL working again. Icestudio complained if I used my clock pad to drive the PLL and something else at the same time, so that was easy to fix. Does it assume that if I use the PLL my FPGA uses the output of the PLL as its internal clock source? I don't know, but it works now.

One other thing I suspect is that I have to re-start Icestudio after adding a collection, otherwise the new collection doesn't show up in the collection manager. Is that normal behavior?

regarding the M1 installation, I have an old MacBook Pro with an Intel processor – I'll install Icestudio on that and see if it behaves differently.

On the positive side, I received my Icebreaker board on Friday, and already, without any previous Verilog experience, I am able to generate test patterns on my Monitor via an DVI interface – that's quite good progress, I would say.

Nigel

[charli va]

Great Nigel! I'm glad to see your progress.

If you want to send us a simple example with the pll issue to see if we can clarify it, I have an icebreaker and I can do tests.

Regarding the collections, I don't know if this week or next I will release a new, much more stable version, right now there is no need to restart but it takes a while to refresh, restarting forces that refresh, a little patience and soon we will have a super manager :)

As soon as I have the new version of the installer for OSX, I will let you know here so you can try it.

Regarding the DVI, if you start it and make a block, share it if you feel like it here, another thing I'm working on that will come with the new collection manager is that we can share designs and blocks from icestudio without needing github, Together we are going to build something very big!

Thank you for using icestudio and sharing your experiences.

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[Nigel Smith]

Hi Charli,

Attached is the build error I get if I try to use the clock input to drive my PLL and something else. Do you have any idea why this error message is being generated?

Regards,

Nigel

[Obijuan]

Hi Nigel!

Here is somethimg that you could try: remove the wire  between CLKIN and CLKIN_COPY. I am not sure if it will work

If it does not work, please send us the .ice file so that we can test it locally in our boards

Best regards, Obijuan

[Nigel Smith]

Obijuan,

I've already tried that (see my previous messages) and it does stop the build error, but I'm trying to understand what the problem is.

Regards,

Nigel

[Obijuan]

Hi Nigel,

If you could provide your .ice it would be easier to detect the problem.  Try to reduce the circuit to the minum that generate the error

Best regards, Obijuan

[charli va]

Hi Nigel! what Icestudio version has you installed? Try the last WIP download from https://downloads.icestudio.io and when you have installed , install the development toolchani, (should appear apio 0.9.0)

If you are working in this wip and apio version, forget the previous line XD 

I'll try to reproduce it and tell you.

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[Nigel Smith]

Here's the smallest file that generates this error.

[Nigel Smith]

I'll try the new version (I'm on 0.8.4) when I get a chance (maybe tomorrow). Right now, I'm trying to figure something else out, and I don't want to interrupt the flow...

[charli va]

Hi Nigel, i  am researching in your problem, i never use the original clock and generated by a pll at the same time and never have this case, for this i had been needed to research a little.

Reading Lattive ice40 documentation and digging in other forums i  have learn that you can’t feed the clock net to both the PLL and to internal logic. it's not supported by the iCE40. Basically the input buffer of pin 36 of the FPGA can either be connected to a global clock network to drive logic, or to the PLL but not both at the same time.

Exists other primitive : SB_PLL40_2_PAD:

https://github.com/YosysHQ/arachne-pnr/blob/master/tests/simple/sb_pll40_2_pad.v

 This have two possible outputs:

• PLLOUTGLOBALA  : the new clock
• PLLOUTGLOBALB : the original clock but buffere throught the PLL

In resume, if you don't need the original clock, remove this output, if you needed, use the second primitive.

Tell us about your tests, we learn a lot of every success and every failure.

Thanks for share!

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[charli va]

Sorry i wrong the clock fpga pin number for the icebreaker, this is 35 not 36.

[Nigel Smith]

Thanks guys, this is interesting stuff. I've been reading a bit more about using the PLL in the Ice40, and I have another question: How can I configure Icestudio to use the PLLOUTGLOBAL signal as the system clock? According to the Ice40 data sheet, this should be possible and is considered a normal use case, but how do I do it? Ideally, I want to have a design in Icestudio that uses a PLL to generate a new system clock – 24 MHz, say – and in every module where "clk" is referenced, this 24-MHz clock is used instead of the 12-MHz clock on pin 35. This seems like a perfectly normal thing to do, but I can't figure out how to do it. Is there (or should there be) a design-level setting that tells Icestudio what the source of "clk" is for a particular design?

[charli va]

Hi nigel! if you are agree, i'm sending a new thread to talk about the pll and clocks, because for the subject some community users could not read  this thread and could be very interesting.

In short i'm sending the new thread.

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