adding support for new local board failing with MIG invalid error

[Student_11]

Hello, I am trying to add support for our local KCU105 board. I was able to generate the firesim bitstream but facing error when trying to program the board. I already asked on AMD support got no response unfortunately.

Vivado version: 2023.1

Board: KCU105 evaluation board

I am getting the following message when booting from the configuration memory:

I am trying to connect the KCU105 evaluation board to the PCIe slot of my PC and communicate with the FPGA using XDMA. The design also MIG DDR4

[Xicom 50-46] One or more detected MIG version registers have empty values: MIG properties will not be built. Parameter Map Version: 0, Error Map Version: 0, Calibration Map Version: 0, Warning Map Version: 0

version 2.2 with the following configs:

proc create_ddr { name clk_intf ddr_intf } {

set i [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 $name ] 

set_property -dict [list \ 

CONFIG.C0_CLOCK_BOARD_INTERFACE $clk_intf \ 

CONFIG.RESET_BOARD_INTERFACE {reset} \ 

CONFIG.C0_DDR4_BOARD_INTERFACE $ddr_intf \ 

CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ 

CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \ CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ 

CONFIG.C0.DDR4_AxiAddressWidth {31} \ 

CONFIG.C0.DDR4_EN_PARITY {true} \ 

CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \ 

CONFIG.Debug_Signal {Disable} \ 

CONFIG.C0.DDR4_AxiDataWidth {256} \ 

CONFIG.C0.DDR4_DataWidth {64} \ 

CONFIG.C0.DDR4_InputClockPeriod {3332} \ 

CONFIG.C0.DDR4_DataMask {DM_DBI_RD} \ 

CONFIG.C0.BANK_GROUP_WIDTH {1} \ 

] $i 

return $i } 

set ddr4_0 [ create_ddr ddr4_0 default_sysclk_300 Custom]

I had 3 options for the ddr_intf argument for the DDR4 IP: ddr4_sdram_DR, ddr4_sdram_062 and Custom. Because I needed XDMA in my design and because the data width of the XDMA is limited to 256-bits for KCU105, I had to use the Custom ddr4 interface to have the 256-bits (I also wanted to avoid AXI data width converters) because the other two were preset to have an AXI width of 512-bit and cannot be changed.

So, I then I created bitstream and .mcs file with the following configurations:

set_property CONFIG_VOLTAGE 1.8 [current_design] 

set_property CFGBVS GND [current_design] 

set_property CONFIG_MODE {SPIx4} [current_design] 

set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]; # Golden image is the fall back image if new bitstream is corrupted. set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] 

set_property BITSTREAM.CONFIG.CONFIGRATE 69 [current_design]; #Expecting type 'enum' with possible values of '3,6,9,12,22,33,40,50,57,69,82,87,90,110' 

set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] 

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] 

set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] 

set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] 

set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]

Finally when programing flash with the .mcs and after power cycling the board and booting from the config memory, I will receive that message.

In the kcu105 (1.7) board files, namely the preset.xml file, I noticed that the ddr4 IPs have two different proc_names:

"ddr4_sdram_preset_DR"

which has the memory part of: "EDY4016AABG-DR-F"

and "ddr4_sdram_preset_062"

which has the memory part of: "MT40A256M16LY-062E"

and nothing for Custom.

Then when I looked at KCU105 user guide, it seems that memory part is: "MT40A256M16GE-083E"

So I just modified the preset.xml by adding the following (and changed other board files accordingly):

<ip_preset preset_proc_name="ddr4_sdram_preset_custom"> <ip vendor="xilinx.com" library="ip" name="ddr4"> <user_parameters> <user_parameter name="CONFIG.C0.DDR4_MemoryPart" value="MT40A256M16GE-083E" /> <user_parameter name="CONFIG.C0.DDR4_DataWidth" value="64" /> <user_parameter name="CONFIG.C0.DDR4_TimePeriod" value="833" /> <user_parameter name="CONFIG.C0.DDR4_InputClockPeriod" value="3332" /> <user_parameter name="CONFIG.C0.DDR4_AxiAddressWidth" value="31" /> <user_parameter name="CONFIG.C0.DDR4_AxiDataWidth" value="256" /> <user_parameter name="CONFIG.C0.BANK_GROUP_WIDTH" value="1" /> <user_parameter name="CONFIG.C0.DDR4_EN_PARITY" value="true" /> <user_parameter name="CONFIG.C0.DDR4_DataMask" value="DM_DBI_RD" /> <user_parameter name="CONFIG.Debug_Signal" value="Disable" /> <user_parameter name="CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ" value="100" /> <user_parameter name="CONFIG.C0.DDR4_AUTO_AP_COL_A3" value="true" /> </user_parameters> </ip> </ip_preset>

I thought this will fix the issue but I am still getting it. Could you please tell me what might be the cause and why I am getting this? Is there a chance that my board is broken? any comments would be really appreciated.

I also set all the switches of SW15 on the kcu105 board to OFF as instructed in the user guide. Also a screenshot of the block diagram is attached. ​

I also tried using the default MIG DDR4 configurations and using axi data width converter and got the same error.

[Muhammad Ali Akhtar]

have you tried to interface with DDR4 outside of firesim? By just creating an example MIG and read / write to DDR4

secondly, what happens if you do not use board files at all?. I mean, just select fpga part and manually add xdc file for pin assignment

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Muhammad Ali Akhtar
http://www.linkedin.com/in/muhammadakhtar