Re: Digest for electricvlsi@googlegroups.com - 3 updates in 2 topics

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Alexandre Rusev

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Jun 11, 2021, 4:42:24 AM6/11/21
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Hello all!


Adam made initial implementation of SkyWater130 support.
This is just a generator of XML description file, written in Java.

Since then I learned (thanks to Steven) how to edit electric technology file manually.
I'm not sure that generating tech file with a program or script is good idea, may be that's because of
I do not have real understanding of technology designed by Adam.

You need to learn SkyWater  manuals to code it in XML file.
The result needs to be tested simultaneously (check that DRC works accordingly thech manual)

If somebody from academia has students to help this work you are wellcome
 

But the generated tech file is incomplete and not tested yet.
I can't do this work quickly myself 


Other people in this list who are make also some effort for support of technologies (likes Sky130)
in Electric:
 Estevao Teixeira est...@engenharia.ufjf.br
 Joselito Morallo jpmo...@gmail.com




On Thu, 24 Sep 2020 02:00:28 -0700
Adam Joseph <ad...@westernsemico.com>  wrote:
> Please don't hand-edit the XML file, it is generated by Java code. I
> will be open-sourcing the generator (Apache license), hopefully this
> weekend, as soon as I purge it of anything covered by the NDAs I have
> with other foundries. I will set up a git repository; once I do that
> you can submit patches against that if you find bugs or want to add
> features.

I have posted the Java code that produces skywater130.xml here on
gitlab:

https://gitlab.com/westernsemico/com.westernsemico.vlsi

On Fri, Jun 11, 2021 at 9:30 AM <electr...@googlegroups.com> wrote:
shalan <msh...@aucegypt.edu>: Jun 09 09:36PM -0700

Hi All,
 
What is the latest stable release of electric and where to find it.
 
Also, what is the current status of Sky130A PDK support.
 
Thanks.
 
--shalan
Gavin Abo <gabo...@gmail.com>: Jun 10 07:24PM -0600

As far as I know, Electric 9.07 released in 2016 is still the latest
stable binary release, which is at:
 
https://www.staticfreesoft.com/productsFree.html
 
However, it looks the source code in the trunk has some changes from 4
weeks ago:
 
http://svn.savannah.gnu.org/viewvc/electric/
 
That source code is likely stable but you would have to build the code.
 
The different build methods for the code are described at:
 
https://www.staticfreesoft.com/jmanual/mchap01-04-01.html
 
I'm not aware of the current status of the Sky130A PDK support. If one
of the others in the list is using that, they might answer you later
about that.
 
Kind Regards,
 
Gavin
 
On 6/9/2021 10:36 PM, 'shalan' via Electric VLSI Editor wrote:
Alexandre Rusev <cybe...@gmail.com>: Jun 10 02:08PM +0300

The more people ask mosis to support Electric the better;)
 
>2. The lowest technology lambda is 200nm for mocmos on electric. Can I
>import a sub-100nm technology from somewhere? If so, how?
 
What you need is to set lambda to 100nm in Electric and fix DRC rules there
accordingly to values specified in the DRM supplied with your PDK ;)
 
 
 
 
On Thu, Jun 10, 2021 at 9:30 AM <electr...@googlegroups.com> wrote:
 
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Alexandre Rusev

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Jun 17, 2021, 4:25:55 AM6/17/21
to electr...@googlegroups.com
>They certainly don't recognize resistive poly layers.
Okay, I'll think on approach to  add this feature. I need to understand algos of resistor parasitic capacitance
extractions, used by other tools...
Is the technology->factors->Minimum Resistane the value presumed to be used for
splitting resistors into "lumped resistor elements" before inserting parasitic capacitors to ground?






On Thu, Jun 17, 2021 at 9:30 AM <electr...@googlegroups.com> wrote:
Alexandre Rusev <cybe...@gmail.com>: Jun 16 10:23PM +0300

Do we have parasitic capacitance extraction for resistors?
 
Thought technology defend parasitic capacitance for resistive poly layer I
don't see parasitic capacitance lumped elements for reistors in spice
netlist.
 
Am I doing something wrong or this feature is not supported now?
 
 
The reason why I need them is following:
We are working on multiphase ring oscillators with resistive feedbacks.
These oscillators are used for building picotimers so they are running at
critical speeds (likes 2.5GHz for 180nm process), so post layout simulation
which takes into account resistors parasitics caps is very important for us.
Steven Rubin <str...@rulabinsky.com>: Jun 16 12:35PM -0700

Support for parasitics in the Spice decks is weak. There are a two
options in the "Spice/CDL" Preferences: "Trans area/perimeter only" and 
"Conservative RC". Neither is as good as you probably want, and they may
not work on resistors at all. They certainly don't recognize resistive
poly layers.
 
   -Steven Rubin
 
On 6/16/2021 12:23 PM, Alexandre Rusev wrote:
student_learner <bibin....@gmail.com>: Jun 16 03:14AM -0700

Hi ,
 
When i tried manually bring the transistors closer, it is resulting in DRC,
however when i tried it using the compact option it is not leading to DRC
problem the optimal area as per expectation. Same problem is seen even
when i integrate 2 block level layout designs. If i try manually, tool says
drc problem and it wont allow to bring the block levels closer (This always
leaves a gap between the block level design in the top level), but when i
do the compaction it is able to get it with the minimum area. What could
be the reason why tool is erroring out when the modules are moved closer
manually, and how is compact helping this. Is this a bug in electric by any
chance or I'm i missing something.
 
I can share snapshots if required.
 
Regards,
Bibin
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