Re: Digest for electricvlsi@googlegroups.com - 2 updates in 1 topic

[Alexandre Rusev]

 Thanks.

So ... looks like that  I need to simulate extracted schematics due to achieve this?

I mean adding PD=.., PS=..., ... to output spice models

Didn't see such behavior  at least when spice code is added to layout cell instead of schematics.

May be I need to learn this magic HOWTO from manual ...

So is the keypoint a simulation of extracted netlist?

And back annotation of these parameters  from layout to schematics could be a good idea as wheel, if come people annotate

PD,PS and so on to schematic symbol of "custom transistor' in tanner tools. Not sure yet.

On Mon, Oct 28, 2019 at 9:30 AM <electr...@googlegroups.com> wrote:

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• Digest for electr...@googlegroups.com - 2 updates in 1 topic - 2 Updates

Digest for electr...@googlegroups.com - 2 updates in 1 topic

Alexandre Rusev <cybe...@gmail.com>: Oct 27 01:12PM +0300 When I write SPICE deck from schematics I see only W, H As I understand for calculating for example area source and perimeter (AS,AD) the SPICE writer needs to know geometry of transistor or presume some default geometry. Out analog designers used to set up AS=.. AD=... with formulas calculating them from W,H and their particular MOSFET geometry. (they are often using ring transistors in 180nm tech)   Okay, if Electic is able to calculate these additional parameters in some cases, then guess it must be using extraction from layout to extimate areas and perimeters, am I right?

Steven Rubin <str...@staticfreesoft.com>: Oct 27 09:27AM -0700 Yes, it does examine all of the cell's geometry to calculate areas and perimeters.      -Steve   On 10/27/2019 3:12 AM, Alexandre Rusev wrote:

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[Steven Rubin]

Area and perimeter information is automatically extracted when writing Spice decks. You may have to fiddle with the "Parasitic" preferences and make sure the Spice preferences set parasitics to "Trans area/perim only".

   -Steve

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