Help with enhancement of layout generation using Silicon Compiler on Electric

[Patrick Mendes]

Hello everyone,

I have written Verilog and VHDL codes for a NAN2 gate and for a nand-based SR flip-flop (static). The codes were checked and work. Just instantiation of the nand2 gates inside the SRFF. With the codes I was able to generate the layout of the SRFF automatically using the Silicon Compiler but with one side effect for each type of HDL:

• Verilog-coded cells: Using the path detailed in the manual throughout the Rats-Nest generation -> Placement -> Routing, the silicon compiler did what I wanted in the way I wanted: two nand2 gates placed side-by-side (one row) and perfectly connected. BUT, the silicon compiler created another layout view of the nand2 gate completely empty with only the exports, besides of the fact it used the layout of them that I had done before. Tried different codings of the nand2 gate and I couldn't get rid of that second layout view. It's worth noting that I only could generate the SRFF layout once I've used the .port_name type instantiation and also providing two extra ports vdd and gnd, because, otherwise, Electric wouldn't connect the vdd's and gnd's of the 2 nand2 gates. The messages window shows the errors bellow but I couldn't solve them nor with the coding nor with the preferences, despite the fact that the layout was concluded:
• Compiling Verilog in cell 'std_ffrs_st_h{ver}' ...
  
• Creating cell std_ffrs_st_h{lay}
• Placed 2 instances <<<------ Placing the already done NAND2 layouts
• Cannot create arc schematic:wire from (78.5,52.5) to (73.5,52.5) in cell 'std_ffrs_st_h{lay}' because the 'from' port (B on node std_nand2{lay}[U2]) does not connect to arc schematic:wire
• Cannot create arc schematic:wire from (8.5,27.5) to (3.5,27.5) in cell 'std_ffrs_st_h{lay}' because the 'from' port (A on node std_nand2{lay}[U1]) does not connect to arc schematic:wire
• Created 4 wires <<<------ Connecting correctly Q, QB, vdd and gnd, even after the last two messages.
• Creating cell std_nand2{lay} <<<-------- Here is the problem: recreating an already placed layout! I can't understand this!!!
• Done, created std_nand2{lay}
• VHDL-coded cells: the Rats-Nests didn't work (several Java errors that, honestly, I can't understand). But I've managed to have the layout generated simply from Silicon Compiler > Convert Current Cell to Layout. No intermediate steps, one click and voilà: the layout is there. BUT the generated layout wasn't space-saving as the one achieved with the Verilog-coded cell. Electric created a layout in two rows, one port in each row, clearly consuming much more area than the Verilog-coded one. It's less annoying than the other layout, since, it seems to me that if I design a full-adder using the Verilog I'll have to get back to each standard cell or module instantiated and delete that second layout view. Really annoying.

Both resulting layouts are in the figure attached to this post.

I really wanted to proceed with the design using the Verilog, not only because of the resulting layout but also because, to me, it's more intuitive and easy to deal language. I also think VHDL is too wordy.

It's worth noting also that:

• I've tried each and every option on the Tools > Verilog preferences none of them could solve the second layout for the standard cells.
• Each standard cell was design and tested (schematic, layout and verilog views) without any DRC, LVS and Well check errors. Their exports were all checked to be sure they were correctly set is input/output/power/ground.
• In the Verilog view I've coded the vdd and gnd as inout ports to get them connected on the SRFF layout.
• I've read the so many times mentioned post: "Physical Design from Verilog File to synthesis - floorplanning - placement" posted by Gavin. I've followed the instructions for the inverter cell which worked perfectly but served nothing for the nand2 gate of the sclib: it didn't recognized it's own exports.
• I've tried the nor2 version of the SRFF and the problems/errors were the same.

I'm starting to think that, for keeping Electric as my design basis software (I do like Electric, for good) I'll have to migrate to VHDL and be less stressed with the area consuming layout generated through the Silicon Compiler. But, before this, I decided to ask for help first.

After reading lots of manuals, pages, tutorials and books I couldn't get the automated layout generation on Electric that I wanted. Maybe I'm missing some preferences to get what I want. The Verilog and VHDL codes of the cells are in the sequence.

I thank for any answer in advance. Any help would be very nice and appreciated. 

Best regards, Patrick.

VERILOG CODES:

-------------------------------------------

- NAND2:

module std_nand2(A, B, Y, vdd, gnd);

  input A, B;

  output Y;

  inout vdd, gnd;

  wire A, B, Y, vdd, gnd;

  assign Y=~(A && B);

  

endmodule   /* std_nand2 */

- SRFF:

module ffrs_st_h(R, S, Q, QB);

  input R;

  input S;

  output Q;

  output QB;

  wire R, S, Q, QB, vdd, gnd;

  std_nand2 U1(.A(S), .B(QB), .Y(Q), .vdd(vdd), .gnd(gnd));

  std_nand2 U2(.A(Q), .B(R), .Y(QB), .vdd(vdd), .gnd(gnd));

endmodule   /* std_ffrs_st_h */

-------------------------------------------

VHDL CODE:

-------------------------------------------

- SRFF:

entity std_ffrs_st_h is 

  port(R: in BIT; S: in BIT; Q: out BIT; QB: out BIT);

end std_ffrs_st_h;

architecture Structure of std_ffrs_st_h is

  component std_nand2 port (A: in BIT; B: in BIT; Y: out BIT); end component;

  begin

  U1: std_nand2 port map (S, QB, Q);

  U2: std_nand2 port map (R, Q, QB);

end Structure;

[Steven Rubin]

It's that "assign" statement. It's behavioral Verilog, and Electric can't handle that. Only structural Verilog works. Sorry.

   -Steven Rubin

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[Patrick Mendes]

I've done without it as well. Same error. But it does compile with assign since I'm using the "Use ASSIGN Construct" marked on Preferences > Tools > Verilog. It didn't compile without that mark or using an assignment to a variable that is not a wire. 

As I said, I've tested at least 10 different versions of the Verilog code. About 6 were correctly compiled but all with that side effect of regenerating an already made layout. But thank you, Steven, for your answer. I do appreciate your attention. Best regards, 

Patrick.

To view this discussion on the web visit https://groups.google.com/d/msgid/electricvlsi/c3a86d32-aa58-4707-5bf9-f25ee58bf420%40staticfreesoft.com.

--

Patrick Mendes dos Santos, Professor, M.Sc.

Departamento de Engenharia Elétrica / Electrical Engineering Department

Federal Center for Technological Education of Minas Gerais (CEFET-MG).

Campus II, Av. Amazonas, 7675, Nova Gameleira. CEP: 30510-000.

Belo Horizonte, Minas Gerais. Brazil.

Phone: +55  31 3319 6834. 

e-mail: patric...@gmail.com

Website: http://www.eng-eletrica.bh.cefetmg.br/