Layout of Photodiode and PhotoVoltaic

[robb...@gmail.com]

Hello!. 
I'm Designing a cell of photodiode and photovoltaic using electric. I want to ask a few questions and Help how to design:
1. Any example in the electric about the simple layout of a photodiode?

2. Is the library mocmos support to drawing  photodiode or photovoltaic?
3. Which layer in electric to draw P+, N+, Nwell, and Pwell?

Below, I attach the reference image that I used from the article entitled  : Self‐Powered Implantable Medical Devices: Photovoltaic Energy Harvesting Review

[Steven Rubin]

Electric has a Photonics technology that is able to work with light waveguides. The technology doesn't align with any existing fabrication because it's for illustration purposes only. However, it does include some of the "mocmos" (MOSIS CMOS) electrical wires, so it's a good starting place for what you want.

   -Steven Rubin

[robb...@gmail.com]

Ok thanks Steven. But my other question  Which layer is electric to draw P+, N+, Nwell, and Pwell?. 

   

[Steven Rubin]

This is an issue for the specific fabrication you intend to use. Generally, the Select and Well layers are part of the Active wires, Transistors, and other elements that need Select and Well surround. This is the "Electric way" to let designers use higher-level "nodes and arcs" when doing layout, and having those high-level elements include the necessary low-level ones (such as Well). So you DO have to create these layers, and assign them fabrication labels (GDS, etc.) then use them when constructing your higher-level elements. But the specifics are given by the foundry, not me.

   -Steven Rubin

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[robb...@gmail.com]

The designs I make are for educational purposes only, not for fabrication or tapeout. So, my purpose is to learn how to make a photodiode or photovoltaic layout with a generic library.

[Joselito Morallo]

Hello! I am reading this thread about photodiode, I have done some layout of chips way back in 1997 about four chips from ROHM on a 250um process but that was long time ago. I only recall when you do the chip it should be coomplety symmetric, devices and pads.

I suggest if you can use the open source 130nm skywater, 180nm IHP, GF90nm process so we can collaborate how we can migrate these process to electric.

Best Regards,

Joselito

RISCV SoC Advocate

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[Alexandre Rusev]

What simulators are used for photonic elements?

They probably need to  interact with SPICE ...

Are that photonic components modelled as lumped elements or distributed

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