EDA Playground now supports ALL SystemVerilog features

[Victor Lyuboslavsky]

EDA Playground now supports ALL SystemVerilog features, including randomization, functional coverage, and SystemVerilog assertions. This has been our biggest goal for over a year, and we're happy to finally reach it.

Examples
Randomization: http://www.edaplayground.com/x/2Xh
Functional Coverage (with SVUnit): http://www.edaplayground.com/s/example/206

Read more here: http://eda-playground.readthedocs.org/en/latest/riviera-pro.html

-Victor

[Anderson Venturini]

Great news! Congratulations for the amazing job, Victor.

[David Rogoff]

This is fantastic!  Thanks so much for providing this.

 David

[Suresh Kumar]

Thanks a lot for the full feature set. Is it possible to set options for FCOVER to display the 'fcover.acdb' data base or to suppress the warnings etc.? Please see http://www.edaplayground.com/x/Pwv

[Suresh Kumar]

Could not open .acdb with http://sqlitebrowser.org/

[Victor Lyuboslavsky]

+Sunil from Aldec

Sunil,

Can you comment whether it is possible to view the coverage *.acdb file with any free tool?

Alternatively, is there a switch users can add to generate a text coverage report?

Thank you,

Victor

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[chig...@gmail.com]

On Wednesday, October 22, 2014 3:17:12 PM UTC+1, Victor Lyuboslavsky wrote:

Can you comment whether it is possible to view the coverage *.acdb file with any free tool?

Alternatively, is there a switch users can add to generate a text coverage report?

acdb report -db <name>.acdb -txt -o <report_file>.txt 

I would have thought that on EDAPlayground you'd want to generate the HTML and serve that?

acdb report -db <name>.acdb -html -o <report_file>.html

Thanks,

Chris 

 

[Victor Lyuboslavsky]

Yes, displaying a coverage HTML report on the list of future features to be added.

-Victor

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[Suresh Kumar]

Hi Victor,

Please see http://www.edaplayground.com/x/96S and help me to resolve the scripter error showing while trying to use acdb report -db <name>.acdb -txt -o <report_file>.txt 

Suresh

[Yi Wang]

How do I run SystemVerilog + DPI on EDAPlayground?

[Victor Lyuboslavsky]

There is a ModelSim example in the Examples section of the left panel: http://www.edaplayground.com/x/3Uh

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[Yi Wang]

Thank you!  

Noticed that the extension must be .cc and that makes it necessary to use extern "C" to wrap around codes even if they are just purely C.

It would be simpler if .c is supported as well.

BTW, no way to run it in Riviera?  Anyways, love edaplayground.

[Vinay Jain]

Hi Victor,

I am trying to create Multi-dimension array example for my team but its say " ERROR VCP5211 "Aggregate literal is not allowed in this context." "testbench.sv" 22 7"

http://www.edaplayground.com/x/BJF 

I compiled same code using VCS and its compiled and simulate. But EDAplayground is giving me error. Would you plz check.

Kind Regards,

Vinay Jain.

[EDA Playground]

Hi Vinay Jain,

Just for your information, EDA Playground is now maintained by Doulos. Doulos is an independent training company for SoC, FPGA and Embedded system design.

According to the LRM, I think your example is illegal syntax. As you have discovered, Riveria Pro rejects it, but VCS does not. I tried it on Questa and got a warning rather than an error.

To make the syntax legal, the outer dimension also needs to be an assignment pattern rather than a concatenation. I have added a ' before the first brace (and some extra comments for explanation) here:

http://www.edaplayground.com/x/CX2

I hope this helps.

Best regards,

Matthew Taylor

Senior Member of Technical Staff

Doulos

[Vinay Jain]

Hi Matthew ,

Thanks I understood now. 

[nanda fathurrahman]

Hi Victor,

the Edaplayground is an awesome work!
Is it possible to use VHDL design file with SystemVerilog testbench?
I cannot find the option in the left hand side menu.

Best regards,
Nanda

[Victor Lyuboslavsky]

Hi Nanda,

This feature is not natively supported yet, and we haven't explored how to do this yet.

It may be possible to do it using the run.do Tcl file

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