Using bidirectional bits in Verilog module

[Tapajara]

I have tried to use bidirectional bits (inout) in a Verilog module that many Verilog simulators flag as illegal L-Values. This does not make sense if you really intend to support bidirectional interface parameters. In order for bits to be birectional, you have to be able to input from them and output to them. I use an input selector that defines when it is to be used for input (Write) and when it is to be used for output (Read). Veritak does not flag an error, but Veritak seems to do minimal checking and doesn't complain even when it should. For example, you can use a "wire" that is not declared anywhere but can use it in an expression and Veritak doesn't care. So why have "inout" if you can never output to it? It seems to either be a flaw in Verilog itelf or an incorrect implementation by those who wrote the simulator. Here is an example:

//Data Register Access Module
module TEST
 (
  inout [7:0] Dat,  //Data
  input Idl,           //Select when Low
  input Wri,         //Access Type: 0=Read,1=Write
  input Clk          //Clock
 );

  //Registers
  reg [7:0] Test; //Data Values

  //Not Selected
  always @(posedge Clk) if (Idl)
    Dat = 64'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ;

  //Selected-Write
  else if (Wri)
    Test = Dat;

  //Selected-Read
  else
    Dat = Test;

endmodule

I selected Icarus Verilog 0.9.7 and these are the error messages it produced:

[2021-06-01 11:19:32 EDT] iverilog '-Wall' design.sv testbench.sv && unbuffer vvp a.out
design.sv:16: error: Dat is not a valid l-value in TEST.
design.sv:5: : Dat is declared here as wire.
design.sv:24: error: Dat is not a valid l-value in TEST.
design.sv:5: : Dat is declared here as wire.
2 error(s) during elaboration.
Exit code expected: 0, received: 1
Done

[Stefano Devecchi]

inout cannot be part of a procedural assignment. 

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[Tapajara]

If I then change assignment to "<=" instead of "=" it then complains that " Dat is declared here as wire. "

If I add "reg" to the declaration, then it complains that " design.sv:4: syntax error I give up. "

[EDA Playground]

inouts (and inputs) must be wires. You cannot drive a wire from an always block. So, you need this workaround:

module TEST
 (
  inout [7:0] Dat,  //Data

  ...

  //Registers

  reg [7:0] Dat_int;

  reg [7:0] Test; //Data Values

  //Not Selected
  always @(posedge Clk) if (Idl)

    Dat_int =

  ...

  assign Dat = Dat_int;

One of the great things about EDA Playground is that it is possible to share code by sharing the URL of that code. This is useful when you are asking for someone's help. I could have editted your code to show you what I mean.

Matthew