Hi,
I am trying to control the enable signal going into a block RAM. The following does not seem to work:
```
topEntity = exposeClockResetEnable $ \rden addr -> let
bram = blockRamPow2 (repeat 0 :: Vec 1024 (Unsigned 32))
dout = exposeEnable bram (toEnable $ rden .&&. fromEnable enableGen) addr (pure Nothing)
in dout
```
Examining the output, it seems that rden (eta in the generated verilog) is not routed into the block RAM at all:
```
module topEntity
( // Inputs
input clk // clock
, input rst // reset
, input en // enable
, input eta
, input [9:0] eta1
.
.
.
always @(posedge clk) begin : result_blockRam
if (1'b0 & en) begin
result_RAM[(result_res)] <= ({32 {1'bx}});
end
if (en) begin
result <= result_RAM[(wild)];
end
end
```
However, if I just move exposeEnable around, then I can get rden (eta) routed into the block RAM:
```
topEntity = exposeClockResetEnable $ \rden addr -> let
bram = exposeEnable $ blockRamPow2 (repeat 0 :: Vec 1024 (Unsigned 32))
dout = bram (toEnable $ rden .&&. fromEnable enableGen) addr (pure Nothing)
in dout
```
which synthesizes to:
```
always @(posedge clk) begin : result_blockRam
if (1'b0 & eta) begin
result_RAM[(result_res)] <= ({32 {1'bx}});
end
if (eta) begin
result <= result_RAM[(wild)];
end
end
```
Though not exactly what I expect, it's getting closer. What is the right way to achieve my goal? Any comments or suggestions would be greatly appreciated.
All the Best,
Chen-Mou Cheng