Problem in printing a vector

[zahra]

Hi all,

I'm new to Chisel and for my project I need to make some modifications to the Rocket core. I got an error due to a printf statement in my code, and I can't figure out what the problem is. Any hint on how to fix it would be greatly appreciated.

Here, I have a data array for cache and I need to print the contents of accessed cache blocks for debugging purposes:

val data_arrays = Seq.fill(1) { SeqMem(nSets * 2 , Vec(128 , UInt(width = 8))) }

val data = array.read(addr, valid && !io.req.bits.write)   //based on the data_array implementation, this is expected to return Vec(128 , UInt(width = 8)) //128B

 val Group_32B = data.grouped(32).map(_.asUInt).toSeq   //That accessed 128B is grouped into four 32B values

 printf("%x %x %x %x\n", Group_32B(0), Group_32B(1), Group_32B(2), Group_32B(3)) 

The above printf statement gives me the following errors at the end of the make process of the Rocket emulator:

g++    SimDTM.o SimJTAG.o emulator.o remote_bitbang.o verilated.o verilated_dpi.o VTestHarness__ALL.a   -L/home/zazad/rocket-chip/fpga-zynq/rocket-chip/riscv/lib -Wl,-rpath,/home/zazad/rocket-chip/fpga-zynq/rocket-chip/riscv/lib -L/home/zazad/rocket-chip/fpga-zynq/rocket-chip/emulator -lfesvr -lpthread  -o /home/zazad/rocket-chip/fpga-zynq/rocket-chip/emulator/emulator-freechips.rocketchip.system-DefaultConfig -lm -lstdc++  2>&1 | c++filt
VTestHarness__ALL.a(VTestHarness__19.o): In function `VTestHarness::_sequent__TOP__93(VTestHarness__Syms*)':
VTestHarness__19.cpp:(.text+0xc37e): multiple definition of `VTestHarness::_sequent__TOP__93(VTestHarness__Syms*)'
VTestHarness__ALL.a(VTestHarness__18.o):VTestHarness__18.cpp:(.text+0xbbf6): first defined here
VTestHarness__ALL.a(VTestHarness__19.o): In function `VTestHarness::_sequent__TOP__96(VTestHarness__Syms*)':
VTestHarness__19.cpp:(.text+0xc4cc): multiple definition of `VTestHarness::_sequent__TOP__96(VTestHarness__Syms*)'
VTestHarness__ALL.a(VTestHarness__18.o):VTestHarness__18.cpp:(.text+0xc3d4): first defined here
VTestHarness__ALL.a(VTestHarness__19.o): In function `VTestHarness::_eval(VTestHarness__Syms*)':
VTestHarness__19.cpp:(.text+0xc8c4): multiple definition of `VTestHarness::_eval(VTestHarness__Syms*)'
VTestHarness__ALL.a(VTestHarness__18.o):VTestHarness__18.cpp:(.text+0xc8c4): first defined here
VTestHarness__ALL.a(VTestHarness__19.o): In function `VTestHarness::_change_request_1(VTestHarness__Syms*)':
VTestHarness__19.cpp:(.text+0xd068): multiple definition of `VTestHarness::_change_request_1(VTestHarness__Syms*)'
VTestHarness__ALL.a(VTestHarness__18.o):VTestHarness__18.cpp:(.text+0xd068): first defined here
VTestHarness__ALL.a(VTestHarness__19.o): In function `VTestHarness::_change_request(VTestHarness__Syms*)':
VTestHarness__19.cpp:(.text+0xd0cc): multiple definition of `VTestHarness::_change_request(VTestHarness__Syms*)'
VTestHarness__ALL.a(VTestHarness__18.o):VTestHarness__18.cpp:(.text+0xd0cc): first defined here
VTestHarness__ALL.a(VTestHarness__17.o): In function `VTestHarness::_sequent__TOP__81(VTestHarness__Syms*)':
VTestHarness__17.cpp:(.text+0x7ea0): multiple definition of `VTestHarness::_sequent__TOP__81(VTestHarness__Syms*)'
VTestHarness__ALL.a(VTestHarness__19.o):VTestHarness__19.cpp:(.text+0x1e2): first defined here
VTestHarness__ALL.a(VTestHarness__19.o): In function `VTestHarness::_eval(VTestHarness__Syms*)':
VTestHarness__19.cpp:(.text+0xc9b4): undefined reference to `VTestHarness::_combo__TOP__38(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xca49): undefined reference to `VTestHarness::_combo__TOP__44(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xca51): undefined reference to `VTestHarness::_combo__TOP__48(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcabd): undefined reference to `VTestHarness::_combo__TOP__53(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcb29): undefined reference to `VTestHarness::_combo__TOP__58(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcb95): undefined reference to `VTestHarness::_combo__TOP__62(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcb9d): undefined reference to `VTestHarness::_combo__TOP__64(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcbe0): undefined reference to `VTestHarness::_combo__TOP__67(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcc0e): undefined reference to `VTestHarness::_combo__TOP__70(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcc2b): undefined reference to `VTestHarness::_combo__TOP__74(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcc71): undefined reference to `VTestHarness::_combo__TOP__79(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xce14): undefined reference to `VTestHarness::_sequent__TOP__15(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcef0): undefined reference to `VTestHarness::_sequent__TOP__39(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcf2c): undefined reference to `VTestHarness::_sequent__TOP__49(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcf53): undefined reference to `VTestHarness::_sequent__TOP__54(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcf7a): undefined reference to `VTestHarness::_sequent__TOP__59(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcfa1): undefined reference to `VTestHarness::_sequent__TOP__65(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcfbb): undefined reference to `VTestHarness::_sequent__TOP__69(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcfc8): undefined reference to `VTestHarness::_sequent__TOP__71(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcfd5): undefined reference to `VTestHarness::_sequent__TOP__75(VTestHarness__Syms*)'
VTestHarness__19.cpp:(.text+0xcff7): undefined reference to `VTestHarness::_sequent__TOP__80(VTestHarness__Syms*)'
collect2: error: ld returned 1 exit status
make[1]: Leaving directory '/home/zazad/rocket-chip/fpga-zynq/rocket-chip/emulator/generated-src/freechips.rocketchip.system.DefaultConfig'

[Jack Koenig]

Your code looks fine to me, I tried it on a pretty recent checkout of rocket-chip 50bb13d7887e5f9ca192431234b057ae9d8edb6c and it worked fine.

If you can provide a patch or rocket-chip fork to reproduce, that would be very helpful. It is weird that neither FIRRTL nor Verilator complain and it fails during linking.

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