Running verilated chiseltest outside of sbt?

[Warren Savage]

Is it possible to run this outside of the sbt environment from the shell in test-run-dir?  It seems like you should, but haven't been able to figure it out so far.

It's an odd use case, but my aim is to play around with some black-boxed Verilog code outside the full Chisel environment.

Warren

[Øyvind Harboe]

Yes, this is possible.

You don't say much about your use-case, but you probably need to read up on the Verilator manual.

Let's say you want to:

1. Write a bit of Chisel that uses some existing Verilog code (BlackBox)

2. Write a bit of C++ code that should talk to this Verilog code

3. Then you run Verilator on the all the Verilog code you have and you write a snippet of C++ (per Verilator manual)

Now you can get an exe file that can run the Verilog code and will interact with your C++ program.

This is definitely very common thing to do with Verilator, Chisel and existing Verilog code, so although it is a bit of work, you should find it fairly straightforward.

[Warren Savage]

Hi Øyvind,

Thanks for taking the time to respond. The use case is admittingly unusual.   I am using Chisel to create a synthesizable test bench, with black-boxed Verilog as the DUT.  The simulation is controlled via ChiselTest with the Chisel-generated test bench and the DUT being verilated.

The question was really about whether I could verilate the ChiselTest controller as well.  I suspected not, but wanted to ask the experts.

However, I do have a backup plan in that I also have a Chisel-generated test bench controller with a few simple inputs, like 'clock', 'reset', and 'start', and one output 'done'.  So I think the correct approach is to just verilate those 3 blocks of Verilog (controller, testbench, DUT) and build a little C-wrapper in the normal Verilator way.

BTW, the application for this is something I presented at a government conference last week.  In a nutshell, this thing is used to detect whether a chip has been tampered with.  The Chisel-design is loaded into a big FPGA which is wired up to the suspicious device.  The FPGA applies a gazillion vectors to the device at speed and produces a pass/fail indication at the end.

Thanks again!

Warren

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[Jack Koenig]

I apologize that it took this long for Warren's email to get through. This response was incorrectly tagged as spam (by Google's automation), and I just noticed and let it through. I've promoted Schuyler to moderator to help with this in the future.

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