HI all,
I want to have some test functions as part of a Bundle definition. E.g., having a bus interface and providing read and write functions. I am able to do it on a Module, e.g.,
class CpuInterface(addrWidth: Int) extends Module {
val io = IO(new Bundle {
val cpuPort = new MemoryMappedIO(addrWidth)
})
def read(addr: Int): BigInt = {
io.cpuPort.address.poke(addr.U)
io.cpuPort.wr.poke(false.B)
io.cpuPort.rd.poke(true.B)
clock.step()
// Ignore waiting for a moment
io.cpuPort.rdData.peekInt()
}
However, MemoryMappedIO might be used on other classes that are not a CpuInterface. Therefore, I would like to add it to the Bundle (interface definition). But I need a reference to the Module. I can only do it like this:
class MemoryMappedIO(private val addrWidth: Int) extends Bundle {
val address = Input(UInt(addrWidth.W))
val rd = Input(Bool())
val wr = Input(Bool())
val rdData = Output(UInt(32.W))
val wrData = Input(UInt(32.W))
val ack = Output(Bool())
// TODO: it would fit better here than in CpuInterface, but without a reference to a CpuInterface
def readX(addr: Int, d: CpuInterface): BigInt = {
d.io.cpuPort.address.poke(addr.U)
d.io.cpuPort.wr.poke(false.B)
d.io.cpuPort.rd.poke(true.B)
d.clock.step()
// Ignore waiting for a moment
d.io.cpuPort.rdData.peekInt()
}
}
which is worse, as it contains now a reference to a CpuInterface.
Any good idea to solve this elegantly?
Cheers,
Martin