Documentation for an FPGA workflow?

[Benjamin Ou]

My overall goal is to get synthesizable verilog onto an FPGA (a xilinx VCU118, specifically). I'm more or less a complete beginner at working with FPGAs and with Chipyard, but so far the impression I'm getting from Chipyard documentation is that there's lots of support for testing Chisel chip designs on a simulator, but not much guidance on configuring an FPGA. That said, there does seem to be some references to targeting a VCU118 in the codebase, so I'm wondering if I'm missing some easy existing scripts that spit out whatever files I need for the VCU118 given an existing Chisel generator.

[Alon Amid]

I would recommend trying to follow the relevant pages in the docs, and asking specific question to clarify them: https://chipyard.readthedocs.io/en/latest/Prototyping/VCU118.html

 

Alon

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[Benjamin Ou]

Oh this is perfect; I knew I had to have been missing something simple. Thanks for the pointer.

[Benjamin Ou]

Alright, I installed the Standard Edition (as opposed to Enterprise Edition) of vivado 2021.1 and ran "make SUB_PROJECT=vcu118 bitstream" in the fpga directory and it errored within "fpga-shells/xilinx/common/tcl/prologue.tcl", on the line that executes "create_project -part $part_fpga -force $top". The error reads "Specified part could not be found"; it is immediately preceded by a warning that reads "No parts matched 'xcvu9p-flga2104-2L-e'".

I should also probably note I'm on Ubuntu 16.04.07, and the vivado installation GUI did note that that's technically an unsupported OS for them (although 16.04.05 and 16.04.06 are supported).