How to Implement Custom IP Core?

[Tatsuya]

I want to implement a new IP Core in the chipyard project.

The IP core which I want to implement is Xilinx CAN IP core.

I would be very greteful if you could teach me how to implement this, 

or any good reference on how to implement some IP core in Chipyard.

I have already read and tried Chapter 6, but when converting the IP source code given in Verilog format to chisel in Chapter 6.10, I don't know where to set build.sbt for teapout. 

[Brendon Chetwynd]

Tatsuya,

It may help you some to look at the work we have done with chipyard, which includes a bunch of custom cores as blackbox modules.  This includes modifying build.sbt to pull in those components.

https://github.com/mit-ll/CEP.git

- Brendon

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[Tatsuya]

Hi, Brendon

Thank you for your comments.
I have checked the repository you have advanced.
I understood that the verilog files for the custom IP core are stored in the generator folder.
I also understood that I need to edit the build.sbt.
But I do not know which build.sbt to modify and how.
Do you know of any resources or solutions that might help?

Regards

-Tatsuya

2022年7月15日金曜日 20:51:40 UTC+9 bche...@gmail.com:

[Brendon Chetwynd]

Tatsuya,

Our build process is tweaked a bit from the chipyard default, given that we have an optional internal repository which has not been release.

I'd recommend looking at build.sbt.nonasic... this gets copied to build.sbt as pre-processing step before the main chipyard build.

At the end, we have added our subproject (generators/mit-ll blocks).  This correlates to the import mitllBlocks in CHISEL.  You also note that mitllBlocks has been added to the "lazy val chipyard" dependencies.

Not sure if this answers your question.

- Brendon

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[Tatsuya]

Brendon

Thank you for your contribution.
I guess what you are trying to say.

I will try implementation of CAN IP following your opnion!
When I want to implement some custom IP core, I should make velirog code of instance of IP core, after that I can set I/O pin etc, right?

2022年7月19日火曜日 20:18:37 UTC+9 bche...@gmail.com:

[Brendon Chetwynd]

Tatsuya,

There are many ways to make IP cores within the Chipyard framework: native chisel, blackbox verilog, Xilinx IP, etc.  We chose blackbox verilog.

There are examples of other types within ./generators.

As to I/O...  I assume you mean the I/O of the IP Core, not the overall chip.  In our case, with blackbox verilog, you need to ensure the I/O + module name of your black box match the chisel exactly, otherwise the design will not elaborate properly.

- Brendon

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[Tatsuya]

Thank you for your resoponse.

I'm thinking to use a CAN IP core provided by Xilinx IP.

I will generate a verilog code of the IP core in some way.

After that, I have to convert verilog into Chisel, right?

2022年7月20日水曜日 20:07:45 UTC+9 bche...@gmail.com:

[Brendon Chetwynd]

Tatsuya,

There are examples in the Chipyard framework of integration Xilinx IP.... such as the Xilinx Memory Interface Generator (MIG).

You identify the blackbox in Chisel which provides the connectivity to the verilog module.  The verilog module is defined in a separate file.

Here is an example:

https://github.com/mit-ll/CEP/blob/master/generators/mitll-blocks/src/main/scala/aes.scala\

- Brendon

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[Tatsuya]

I want to be able to connect my new Pmod module to my FPGA board. The PMOD module to be connected must be connected via SPI interface.
So I want to connect the new SPI interface with a vacant PMOD connector.
Does anyone know which part of the description I need to change to create the new SPI interface?
I would be very happy if you could tell me.

2022年7月21日木曜日 9:38:11 UTC+9 bche...@gmail.com:

[Ashbin Shiju]

To add Custom Core into Chipyard :
in the chipyard/generators/mytile/src/main/resources/vsrc
    add the verilog/SV files that you want to integrate .
in chipyard/generators/mytile/src/main/scala
   create files ConfigMixins.scala , mytile.scala, MyTile.scala

    ConfigMixins.scala : This file defines configuration mixins (specifically WithNMyCores), which allow users to easily add specific numbers of MyTile instances to a top-level Chipyard SoC configuration.
    mytile.scala : This file defines the Chisel BlackBox wrapper, which serves as the direct hardware interface allowing Chisel to instantiate, recognize ports for, and link to the underlying
                   Verilog source  code (mytile.v).

    MyTile.scala : This file contains the diplomatic integration and implementation logic, defining the LazyModule and parameters required to connect the custom tile to the Chipyard system bus (via TileLink)
                   and interrupt controllers, while also wiring these system signals to the BlackBox ports.

in chipyard/build.sbt
                  add the mytile along with the remaining tiles.

refer CVA6 for more information.