Removing IO cells

[Kartik Prabhu]

I'm putting ChipTop inside of an existing chip, so I don't want IO cells to be created. Removing the config fragment removes the IO from ChipTop, which is not what I want.

What would be the best way to do this? Create a new passthrough IO cell? I want to still preserve the simulation behavior.

[Jerry Zhao]

You can look at how FireSim sets IOCellKey to use pure passthrough IO cells.

https://github.com/ucb-bar/chipyard/blob/65fae6b77c7774bb2ade283cd26544c5208deaa0/generators/firechip/src/main/scala/BridgeBinders.scala#L41-L69

You can define your own IOCellParams object that references your own set of pure passthrough IOCells, and set IOCellKey accordingly.

On Mon, May 17, 2021 at 1:54 PM Kartik Prabhu <kpra...@stanford.edu> wrote:

I'm putting ChipTop inside of an existing chip, so I don't want IO cells to be created. Removing the config fragment removes the IO from ChipTop, which is not what I want.

What would be the best way to do this? Create a new passthrough IO cell? I want to still preserve the simulation behavior.

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[Kartik Prabhu]

It looks like this does not support DigitalGPIO. Is there a reason why? Ideally I want a ChipTop that looks a lot like DigitalTop.

[John Wright]

The GPIO cell type is for converting the GPIO input, output, and control signals into a single bidirectional (analog) port. If you just want to plumb all of the GPIO signals to the top, you can use multiple DigitalIn and DigitalOut IOCells.

John

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[Jerry Zhao]

GPIO cells are supported through this system. They are just unsupported in Firesim because we don't support simulation of bidirectional ports in Firesim.

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[Kartik Prabhu]

Thanks guys. So the main issue in my design is with the SPIFlash, since it has birdirectional ports. I created a passthrough SPI IO Binder:

class WithPassthroughSPIIOCells extends OverrideIOBinder({

  (system: HasPeripherySPIFlashModuleImp) => {

    val io_pins = system.qspi.zipWithIndex.map { case (s, i) => IO(s.cloneType).suggestName(s"spi_${i}") }

    (io_pins zip system.qspi).map { case (io, sysio) =>

      io <> sysio

    }

    (io_pins.unzip, Nil)

  }

})

And I'm trying to create the corresponding Harness Binder:

class WithPassthroughSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder({

  (system: HasPeripherySPIFlashModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => {

    val (ios: Seq[SPIChipIO], cells2d) = ports.zipWithIndex.map({ case (s, i) =>

      val name = s"spi_${i}"

      val port = Wire(new SPIChipIO(s.c.csWidth)).suggestName(name)

      val iocellBase = s"iocell_${name}"

      // SCK and CS are unidirectional outputs

      val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), system.p(IOCellKey), IOCell.toAsyncReset)

      val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), system.p(IOCellKey), IOCell.toAsyncReset)

      // DQ are bidirectional, so then need special treatment

      val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) =>

        val iocell = system.p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}")

        iocell.io.o := pin.o

        iocell.io.oe := pin.oe

        iocell.io.ie := true.B

        pin.i := iocell.io.i

        iocell.io.pad <> ana

        iocell

      }

      (port, dqIOs ++ csIOs ++ sckIOs)

    }).unzip

    SimSPIFlashModel.connect(ios, th.harnessReset, rdOnly)(system.p)

  }

})

However, the issue here is that the analog can only be bulk connected once, so I have an error with connected the IO pad to the SPI Flash model. Is there an easy way I can just wrap this into a new Module?