coremark.riscv

[ahmad othman]

what is  coremark.riscv? is it a binary code? and can I use it to run Caremark test on rocketchip?

[Abraham Gonzalez]

Hi,

For the most part, binaries labeled `*.riscv` are binaries compiled to run on RISC-V platforms. Yes, this binary can run the CoreMark test on certain RISC-V cores (not just on the Rocket core on the RocketChip SoC).

Also, for future reference, you should put more information in your mailing list questions (what are you doing, what have you done, what do you understand, what you don't, etc). I understand, based on the other mailing list question, that you are referring to the CoreMark binary in the BOOM GitHub organization... but it's best to keep everything together. I think this question would be a good follow-up reply to the other mailing list question so that one "mailing list thread" is CoreMark related.

Hope that helps.

On Wed, Nov 3, 2021 at 12:50 AM ahmad othman <ahmd...@gmail.com> wrote:

what is  coremark.riscv? is it a binary code? and can I use it to run Caremark test on rocketchip?

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Abraham J. Gonzalez

Electrical Engineering and Computer Science Ph.D. Student

The University of California at Berkeley

[ahmad othman]

Hi Abraham,

Thank you for your help Abraham.

My name is Ahmad Othman. and I am doing my master in computer architecture. I am still a rookie in chipyard. 

sorry for the inconvenience I should put more information. what I am trying to do is adding CISC instructions. I am familiar with rocket chip now. I was asking about this file because I wanted to change the binary file so it can accommodate the new instructions. I am just lost there. I have manage to change the rocketchip but I didnt manage to run Coremark on it. I was able to run other benchmarks. but my question is this how can I change the binary so it can have my new instructions.

[Abraham Gonzalez]

Hi Ahmad,

No problem at all! We are happy to have new people try out / use Chipyard. 

First, I would read through all of the Chipyard documentation to be familiar with the difference between Chipyard and Rocket Chip and how to use the infrastructure. 

https://chipyard.readthedocs.io/en/dev/Simulation/Software-RTL-Simulation.html talks about how to run RISC-V binaries on a Chipyard SoC (on a simulator built from the RTL you modified).

I would look at the repo README (https://github.com/riscv-boom/riscv-coremark) to figure out how to build the RISC-V binary (to modify it you can just modify the C code) which you can then run on the simulator mentioned earlier.

Hope that helps.

To view this discussion on the web visit https://groups.google.com/d/msgid/chipyard/90f0ba9a-9f1b-416f-abeb-b7f3ca53ea2an%40googlegroups.com.

[ahmad othman]

Hi Abraham,

Thank you for your help, I want to ask another question.

I was trying to run coremark binary file using the simulator mentioned, but it never ends.

~/chipyard/sims/verilator$ ./simulator-chipyard-RocketConfig  ~/chipyard/software/coremark/riscv-coremark/coremark.bare.riscv
This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.
Listening on port 44507
[UART] UART0 is here (stdin/stdout).

Am I missing something here? And how much it should take time to run it normally?

I appreciate your help and time.

Ahmad

[Abraham Gonzalez]

Hi Ahmad,

I would verify that the binary runs with Spike (the functional simulator)? Additionally, you should try to run binaries with the helper make targets as mentioned in the docs (here when we talk about `make BINARY=binary.riscv run-binary`) so that you can be sure that the sim is run correctly. As for runtime, I don't remember how long it should run for.

Best of luck!

To view this discussion on the web visit https://groups.google.com/d/msgid/chipyard/480312f1-0caa-4fe3-8fe5-89b02fe445d1n%40googlegroups.com.

[ahmad othman]

Hi Abraham,

sorry to interrupt again. I used make binary to run coremark like this:

~/chipyard/sims/verilator$ make BINARY=coremark.bare.riscv run-binary-fast
Running with RISCV=/home/othman/chipyard/riscv-tools-install
(set -o pipefail &&  /home/othman/chipyard/sims/verilator/simulator-chipyard-RocketConfig +permissive +dramsim +dramsim_ini_dir=/home/othman/chipyard/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000   +permissive-off coremark.bare.riscv </dev/null | tee /home/othman/chipyard/sims/verilator/output/chipyard.TestHarness.RocketConfig/coremark.bare.log)

This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.

Listening on port 42713
== Loading device model file '/home/othman/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini' ==

[UART] UART0 is here (stdin/stdout).

== Loading system model file '/home/othman/chipyard/generators/testchipip/src/main/resources/dramsim2_ini/system.ini' ==
===== MemorySystem 0 =====
CH. 0 TOTAL_STORAGE : 4096MB | 1 Ranks | 16 Devices per rank
DRAMSim2 Clock Frequency =666666666Hz, CPU Clock Frequency=100000000Hz
*** FAILED *** via trace_count (timeout, seed 1638251839) after 10000000 cycles
make: *** [/home/othman/chipyard/common.mk:179: run-binary-fast] Error 2

and without the run fast

make BINARY=coremark.bare.riscv run-binary
Running with RISCV=/home/othman/chipyard/riscv-tools-install
(set -o pipefail &&  /home/othman/chipyard/sims/verilator/simulator-chipyard-RocketConfig +permissive +dramsim +dramsim_ini_dir=/home/othman/chipyard/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000   +verbose +permissive-off coremark.bare.riscv </dev/null 2> >(spike-dasm > /home/othman/chipyard/sims/verilator/output/chipyard.TestHarness.RocketConfig/coremark.bare.out) | tee /home/othman/chipyard/sims/verilator/output/chipyard.TestHarness.RocketConfig/coremark.bare.log)

[UART] UART0 is here (stdin/stdout).

make: *** [/home/othman/chipyard/common.mk:175: run-binary] Error 2

so i increased the max-cycles to 5000000000

./simulator-chipyard-RocketConfig +max-cycles=5000000000 coremark.bare.riscv

This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.

Listening on port 38485

[UART] UART0 is here (stdin/stdout).

*** FAILED *** via trace_count (timeout, seed 1638223925) after 5000000000 cycles

I tried to change number of iteration in coremark code but it didnt change anything.

can you please help me with that.

-ahmad