Issue on running CoreMark bare-metal on RocketCore

[Lucas Arruk]

Hi all,

I’m trying to run CoreMark (bare-metal) on the default RocketConfig in Chipyard using the Verilator simulator, and I consistently hit a runtime error: bad syscall #2147500800. I’d appreciate pointers on the correct setup/mixins and the recommended way to run CoreMark on the current Chipyard.

I used the simulation tutorial included on the official documentation, through Verilator (just ran make with the default config of Rocket). After that, entered the software/coremark directory and used the build.sh to compile the benchmark (also tried to use the build-coremark.sh in the riscv-coremark directory). To run the binary (coremark.bare.riscv), I used the run-binary option in make with LOADMEM, and the result was

[UART] UART0 is here (stdin/stdout). 

make: *** [[...]/chipyard/common.mk:319: ../../software/coremark/riscv-coremark/coremark.bare.riscv.run] Error 255

I analyzed the log and the problem was about a bad syscall:

terminate called after throwing an instance of 'std::runtime_error' what(): bad syscall #2147500800

I can provide full logs (.log and disassembly .out) if useful. Thanks a lot for any guidance.

Best,
Lucas

[Junaid amjad]

Hi,
I ran the same test with the default rocket config and it's working fine. Well it did not finish because it's a very long test and takes a very long time to complete but let me share the logs with you

[UART] UART0 is here (stdin/stdout).

2K performance run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 44720386
Total time (secs): %f
Iterations/Sec   : %f
ERROR! Must execute for at least 10 secs for a valid result!
Iterations       : 100
Compiler version : GCC13.2.0
Compiler flags   : -O2 -mcmodel=medany -static -std=gnu99 -fno-common -fno-tree-loop-distribute-patterns -nostdlib -nostartfiles -lm -lgcc -T ../riscv64-baremetal/link.ld  
Memory location  : Please put data memory location here
                        (e.g. code in flash, data on heap etc)
seedcrc          : 0xe9f5
[0]crclist       : 0xe714
[0]crcmatrix     : 0x1fd7
[0]crcstate      : 0x8e3a
[0]crcfinal      : 0x988c
Errors detected
- /home/em/Documents/chipyard/sims/verilator/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/TestDriver.v:158: Verilog $finish


You need to increase the cycle counts in order to let it complete. But the main point is I did not get any error that you mentioned above, maybe just try increasing the timeout and see what happens, thanks!

Regards,
Junaid

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