Hello,
I've been trying to run some of the riscv-tests, but am unable to run anything. I've make sure to build with make prep.
make build.verilator sim.verilator SUITE=riscv-tests PROG=rsort TAG=rsort_test
But ultimately it gets an error:
rm Vtestbench__ALL.verilator_deplist.tmp
make[1]: Leaving directory '/home/jlim/blackparrot/black-parrot-sim/black-parrot/bp_top/syn/results/verilator/bp_tethered.e_bp_default_cfg.rsort_test.build/obj_dir'
- V e r i l a t i o n R e p o r t: Verilator 5.030 2024-10-27 rev v5.030
- Verilator: Built from 5072.089 MB sources in 615 modules, into 228.918 MB in 153 C++ files needing 0.970 MB
- Verilator: Walltime 67.157 s (elab=1.478, cvt=11.338, bld=50.582); cpu 17.376 s on 4 threads; alloced 794.492 MB
- Verilator: Built from 5072.089 MB sources in 615 modules, into 228.918 MB in 153 C++ files needing 0.970 MB
- Verilator: Walltime 67.157 s (elab=1.478, cvt=11.338, bld=50.582); cpu 17.376 s on 4 threads; alloced 794.492 MB
make: *** No rule to make target '/home/jlim/blackparrot/black-parrot-sim/black-parrot/bp_top/syn/results/verilator/bp_tethered.e_bp_default_cfg.rsort_test.sim.riscv-tests.rsort/run_simsc', needed by 'sim.verilator'. Stop.
The sim directory isn't created, but it looks like it properly build the verilator model?
Am I missing something in how to specify other tests? (tried beeps/crc).
Thanks,
Jeffery Lim