Hammerblade on Alveo2

[Amit Hiremath]

Hello Dan,

Sorry to create duplicate thread, whenever I reply to the post, messages are getting deleted I can't pinpoint the reason perhaps admin can.  Following is my response to the thread:  Hammerblade on Alveo

I think,  I am able to successfully run co-simulation example, it is matching with vcs simulation the output of vcs is:

bsg_zynq_pl: Exiting reset
bsg_zynq_pl: Exiting reset
bsg_zynq_pl: Exiting reset
INFO: ps.cpp: reading three base registers
INFO: ps.cpp: dram_base=0
INFO: Creating Bitbang Driver: 0xea8560 40000004 16 1
INFO: Reset Tag Master
INFO: Resetting Tag Client 0
INFO: Setting Tag Client 0<-1
INFO: Setting Tag Client 0<-0
INFO: Idling for 50
INFO: ps.cpp: calling allocate dram with size 134217728
INFO: bsg_zynq_pl: Allocated dummy DRAM
INFO: ps.cpp: received 0x2aaabf8b3010 (phys = 2aaabf8b3010)
INFO: ps.cpp: wrote and verified base register
INFO: Starting NBF load
INFO: ps.cpp: nbf finish command, line 8129
INFO: Waiting for credit drain
[INFO][RX] Unfreezing tile t=19566100000, x= 2, y= 2
INFO: Credits drained
INFO: ps.cpp: Starting scan thread
INFO: ps.cpp: Starting MC i/o polling thread
INFO: Errant request packet: 1260 0

Manycore>> Hello from core 0, 0 in group origin=(0,0).
Manycore>> Values in DRAM:ffffffff,00000001,0000000f,80000000,

Manycore stderr>> Hello!

Interrupt array at 0x0
INFO: MC finish packet received 1
INFO: ps.cpp: Starting BP i/o polling thread
Hello World!
INFO: BP finish packet received 1
INFO: bsg_zynq_pl: done() called, exiting
$finish called from file "/home/sonal/ViBram/zynq-parrot/cosim/v/bsg_nonsynth_zynq_testbench.sv", line 471.
$finish at simulation time 20506525001
V C S S i m u l a t i o n R e p o r t
Time: 20506525001 ps

except that in Alveo I am not getting  Hello World!  it is stuck at  INFO: ps.cpp: Starting BP i/o polling thread

However, I successfully  ran black-parrot-minimal example in Alveo.

I think shell<-->host is proper. I haven't changed in anything hardware designs/DUT, except shell_read and shell_write, which I am communicating through PCIe slot.
For 60MHz, 65Mhz and 75Mhz designs/DUT, I did not get critical timing warnings for timings, however,  I did get  critical timing warnings for 100MhZ design because of clock skew and design/DUT is not meeting timing requirements for 100MHz.

In case of clock domain crossing from PCIe to DUT, I am using clocking wizard IP from vivado, which divides 300MHz PCIe clock to   60MHz, 65Mhz, 75Mhz and 100Mhz or any frequency of your choice.

-Amit

[Dan Petrisko]

The group is moderated, so messages are manually approved. I see all of your duplicate messages.

Sounds like everything is set up correctly on the ZynqParrot side then. The examples work in cosim, on PynqZ2 and on Ultra96v2 boards, and are very stable across clock frequencies. So it is most likely a problem with 1) your PCIE<->shell communication or 2) AXI -> Alveo memory system. This is outside of our scope of support. We do not own an Alveo board nor have other PCIE-based FPGA setups for this infrastructure. If you would like to donate a board to the lab, please message me offline

I would suggest adding an ILA probe to compare the trace of memory accesses between the hardware and simulation. They should match 1:1 as I don't believe there is any timing dependency. Other helpful ILA probes might be the PC of BP or the network ports of BP->MC

-Dan

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[Amit Hiremath]

Thanks Dan got it. On  the other hand, I also tried black-parrot-example on Pynq z2 board, I am not getting output there as well. I am stuck what could be the problem here.