You might help your self by explaining why you might want to do this.
In other words, what is the problem you are trying to solve.
Since 24 MHz is the master clock for the CPU, changing it will break all the
timing systems, time, serial ports, anything using or depending on time or frequency.
And since there are internal PLLs in the Sitara, there are limits as to how
far you can move.
You might be better off designing a little hardware circuit that would
take 12.8 as an input and provide a phase locked 24 MHz as an output.
Or leaving the master clock on the Sitara alone, and learning how to
move data across clock domain boundaries.
--- Graham
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