Debugging SPI device

Yendor

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Jan 19, 2021, 4:24:32 PM1/19/21

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Hi,

Carrying on from the SeeedStudio SenseCAP Gateway hacking form this conversation (https://groups.google.com/g/beagleboard/c/Y_Zx_D2HJUA)

I am now looking to get the LoRa interface working, the interface is a mPCIe SPI RAK2247 LoRa card connector.

The things I think I need to find out how to do:

Identify the correct SPI bus for the connector;
and what GPIO drives the reset pin (PIN 22) of the connector.

if anyone has any ideas on the best why to do this, please feel free to share.

Regards,

result of gpioinfo:

gpiochip0 - 32 lines:

line 0: "MDIO_DATA" unused input active-high

line 1: "MDIO_CLK" unused input active-high

line 2: "SPI0_SCLK" "P9_22" input active-high [used]

line 3: "SPI0_D0" "P9_21" input active-high [used]

line 4: "SPI0_D1" "P9_18" input active-high [used]

line 5: "SPI0_CS0" "P9_17" input active-high [used]

line 6: "SPI0_CS1" "cd" input active-low [used]

line 7: "ECAP0_IN_PWM0_OUT" "P9_42" input active-high [used]

line 8: "LCD_DATA12" "P8_35" input active-high [used]

line 9: "LCD_DATA13" "P8_33" input active-high [used]

line 10: "LCD_DATA14" "P8_31" input active-high [used]

line 11: "LCD_DATA15" "P8_32" input active-high [used]

line 12: "UART1_CTSN" "P9_20" input active-high [used]

line 13: "UART1_RTSN" "P9_19" input active-high [used]

line 14: "UART1_RXD" "P9_26" input active-high [used]

line 15: "UART1_TXD" "P9_24" input active-high [used]

line 16: "GMII1_TXD3" unused input active-high

line 17: "GMII1_TXD2" unused input active-high

line 18: "USB0_DRVVBUS" unused input active-high

line 19: "XDMA_EVENT_INTR0" "A15" input active-high [used]

line 20: "XDMA_EVENT_INTR1" "P9_41" input active-high [used]

line 21: "GMII1_TXD1" unused input active-high

line 22: "GPMC_AD8" "P8_19" input active-high [used]

line 23: "GPMC_AD9" "P8_13" input active-high [used]

line 24: "NC" unused input active-high

line 25: "NC" unused input active-high

line 26: "GPMC_AD10" unused input active-high

line 27: "GPMC_AD11" unused input active-high

line 28: "GMII1_TXD0" unused input active-high

line 29: "RMII1_REFCLK" unused input active-high

line 30: "GPMC_WAIT0" "P9_11" input active-high [used]

line 31: "GPMC_WPN" "P9_13" input active-high [used]

gpiochip1 - 32 lines:

line 0: "GPMC_AD0" "P8_25" input active-high [used]

line 1: "GPMC_AD1" "P8_24" input active-high [used]

line 2: "GPMC_AD2" "P8_05" input active-high [used]

line 3: "GPMC_AD3" "P8_06" input active-high [used]

line 4: "GPMC_AD4" "P8_23" input active-high [used]

line 5: "GPMC_AD5" "P8_22" input active-high [used]

line 6: "GPMC_AD6" "P8_03" input active-high [used]

line 7: "GPMC_AD7" "P8_04" input active-high [used]

line 8: "UART0_CTSN" unused input active-high

line 9: "UART0_RTSN" unused input active-high

line 10: "UART0_RXD" unused input active-high

line 11: "UART0_TXD" unused input active-high

line 12: "GPMC_AD12" "P8_12" input active-high [used]

line 13: "GPMC_AD13" "P8_11" input active-high [used]

line 14: "GPMC_AD14" "P8_16" input active-high [used]

line 15: "GPMC_AD15" "P8_15" input active-high [used]

line 16: "GPMC_A0" "P9_15" input active-high [used]

line 17: "GPMC_A1" "P9_23" input active-high [used]

line 18: "GPMC_A2" "P9_14" input active-high [used]

line 19: "GPMC_A3" "P9_16" input active-high [used]

line 20: "GPMC_A4" unused input active-high

line 21: "GPMC_A5" "beaglebone:green:usr0" output active-high [used]

line 22: "GPMC_A6" "beaglebone:green:usr1" output active-high [used]

line 23: "GPMC_A7" "beaglebone:green:usr2" output active-high [used]

line 24: "GPMC_A8" "beaglebone:green:usr3" output active-high [used]

line 25: "GPMC_A9" unused input active-high

line 26: "GPMC_A10" unused input active-high

line 27: "GPMC_A11" unused input active-high

line 28: "GPMC_BE1N" "P9_12" input active-high [used]

line 29: "GPMC_CSN0" "LS_BUF_EN" output active-high [used]

line 30: "GPMC_CSN1" "P8_21" input active-high [used]

line 31: "GPMC_CSN2" "P8_20" input active-high [used]

gpiochip2 - 32 lines:

line 0: "GPMC_CSN3" unused input active-high

line 1: "GPMC_CLK" "P8_18" input active-high [used]

line 2: "GPMC_ADVN_ALE" "P8_07" input active-high [used]

line 3: "GPMC_OEN_REN" "P8_08" input active-high [used]

line 4: "GPMC_WEN" "P8_10" input active-high [used]

line 5: "GPMC_BE0N_CLE" "P8_09" input active-high [used]

line 6: "LCD_DATA0" "P8_45" input active-high [used]

line 7: "LCD_DATA1" "P8_46" input active-high [used]

line 8: "LCD_DATA2" "P8_43" input active-high [used]

line 9: "LCD_DATA3" "P8_44" input active-high [used]

line 10: "LCD_DATA4" "P8_41" input active-high [used]

line 11: "LCD_DATA5" "P8_42" input active-high [used]

line 12: "LCD_DATA6" "P8_39" input active-high [used]

line 13: "LCD_DATA7" "P8_40" input active-high [used]

line 14: "LCD_DATA8" "P8_37" input active-high [used]

line 15: "LCD_DATA9" "P8_38" input active-high [used]

line 16: "LCD_DATA10" "P8_36" input active-high [used]

line 17: "LCD_DATA11" "P8_34" input active-high [used]

line 18: "GMII1_RXD3" unused input active-high

line 19: "GMII1_RXD2" unused input active-high

line 20: "GMII1_RXD1" unused input active-high

line 21: "GMII1_RXD0" unused input active-high

line 22: "LCD_VSYNC" "P8_27" input active-high [used]

line 23: "LCD_HSYNC" "P8_29" input active-high [used]

line 24: "LCD_PCLK" "P8_28" input active-high [used]

line 25: "LCD_AC_BIAS_EN" "P8_30" input active-high [used]

line 26: "MMC0_DAT3" unused input active-high

line 27: "MMC0_DAT2" unused input active-high

line 28: "MMC0_DAT1" unused input active-high

line 29: "MMC0_DAT0" unused input active-high

line 30: "MMC0_CLK" unused input active-high

line 31: "MMC0_CMD" unused input active-high

gpiochip3 - 32 lines:

line 0: "GMII1_COL" unused input active-high

line 1: "GMII1_CRS" unused input active-high

line 2: "GMII1_RXER" unused input active-high

line 3: "GMII1_TXEN" unused input active-high

line 4: "GMII1_RXDV" unused input active-high

line 5: "I2C0_SDA" unused input active-high

line 6: "I2C0_SCL" unused input active-high

line 7: "EMU0" unused input active-high

line 8: "EMU1" unused input active-high

line 9: "GMII1_TXCLK" unused input active-high

line 10: "GMII1_RXCLK" unused input active-high

line 11: "NC" unused input active-high

line 12: "NC" unused input active-high

line 13: "USB1_DRVVBUS" unused input active-high

line 14: "MCASP0_ACLKX" "P9_31" input active-high [used]

line 15: "MCASP0_FSX" "P9_29" input active-high [used]

line 16: "MCASP0_AXR0" "MCASP0_AHCLKR" output active-high [used]

line 17: "MCASP0_AHCLKR" "P9_28" input active-high [used]

line 18: "MCASP0_ACLKR" "P9_92" input active-high [used]

line 19: "MCASP0_FSR" "P9_27" input active-high [used]

line 20: "MCASP0_AXR1" "P9_91" input active-high [used]

line 21: "MCASP0_AHCLKX" "P9_25" input active-high [used]

line 22: "NC" unused input active-high

line 23: "NC" unused input active-high

line 24: "NC" unused input active-high

line 25: "NC" unused input active-high

line 26: "NC" unused input active-high

line 27: "NC" unused input active-high

line 28: "NC" unused input active-high

line 29: "NC" unused input active-high

line 30: "NC" unused input active-high

line 31: "NC" unused input active-high

Yendor

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Jan 24, 2021, 12:15:27 AM1/24/21

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How can I tell if the SPI interface is enabled?

jonnymo

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Jan 24, 2021, 1:44:57 AM1/24/21

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A quick test is to see if a SPI device has been created under '/dev/'.

A few SPI test references:

https://github.com/derekmolloy/exploringBB/tree/version2/chp08/spi/spidev_test

https://elinux.org/BeagleBone_Black_Enable_SPIDEV

https://gist.github.com/pdp7/33a8ad95efcbcc0fadc3f96a70d4b159

Cheers,

Jon

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Yendor

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Jan 24, 2021, 2:35:38 PM1/24/21

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Thanks for the links Jon,

I see in /dev/spi:

lrwxrwxrwx 1 root root 12 Jan 24 06:30 0.0 -> ../spidev0.0

lrwxrwxrwx 1 root root 12 Jan 24 06:30 0.1 -> ../spidev0.1

lrwxrwxrwx 1 root root 12 Jan 24 06:30 1.0 -> ../spidev1.0

lrwxrwxrwx 1 root root 12 Jan 24 06:30 1.1 -> ../spidev1.1

config-pin give a error

ERROR: open() for /sys/devices/platform/ocp/ocp:P9_17_pinmux/state failed, No such file or directory

and for spi_test on /dev/spidev0.0 to 1.1 with shorting the mosi and miso pins, I get:

sudo ./spi_test --device /dev/spidev0.0

spi mode: 0

bits per word: 8

max speed: 500000 Hz (500 KHz)

00 00 00 00 00 00

00 00

Yendor

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Jan 27, 2021, 3:44:35 PM1/27/21

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How to setup pins as SPI?

Support has let me know what pins are controlling the SPI bus for the LoRa connector and now I need to know how to set them up so they work as SPI0.0

the known pins:

MCASP0_ACLKX gpio3_14 110 SPI1_SCLK

MCASP0_FSX gpio3_15 111 SPI1_DO

MCASP0_AXR0 gpio3_16 112 SPI1_D1

GPMC_A11 gpio1_27 59 LoRa_CS1

after getting this working I would like to write a dts that enables the ethernet, set the spi correctly and enables LoRa (set gpio0_22 as a output and set high), what are the best resources for doing this?

Regards,

Yendor

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Jan 27, 2021, 7:04:33 PM1/27/21

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Copying from https://elinux.org/BeagleBone_Black_Enable_SPIDEV I came up with

------------------------------

/dts-v1/;

/plugin/;

/* SPI1 */

/* D1 Output and D0 Input */

/ {

compatible = "ti,beaglebone", "ti,beaglebone-black", "beaglebone-green";

/* identification */

part-number = "spi1mux";

fragment@0 {

target = <&am33xx_pinmux>;

__overlay__ {

spi1_pins_s0: spi1_pins_s0 {

pinctrl-single,pins = <

0x190 0x33 /* mcasp0_aclkx.spi1_sclk, INPUT_PULLUP | MODE3 */

0x194 0x33 /* mcasp0_fsx.spi1_d0, INPUT_PULLUP | MODE3 */

0x198 0x13 /* mcasp0_axr0.spi1_d1, OUTPUT_PULLUP | MODE3 */

0x6c 0x17 /* gpmc_a11.gpio1_27, OUTPUT_PULLUP | MODE7 */

>;

};

fragment@1 {

target = <&spi1>;

__overlay__ {

#address-cells = < 0x01 >;

#size-cells = < 0x00 >;

status = "okay";

pinctrl-names = "default";

pinctrl-0 = <&spi1_pins_s0>;

spidev@1 {

spi-max-frequency = < 0xf42400 >;

reg = < 0x00 >;

compatible = "linux,spidev";

};

------------------------------
and compiled to dtbo, add to uEnv.txt rebooted but still no reflection when test the SPI, hmmm? don't know if this is been overwritten or just not working?

what the best way to track down what pin are been connected to the SPI bus, I'm thinking I should be able to find what pin are controlling the SCLK, MOSI and MISO.

Regards,

Yendor

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Feb 4, 2021, 4:42:32 PM2/4/21

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I think I see the problem, but don't know how to fix it.

when looking at dmesg or running the version script I see

[ 0.938342] pinctrl-single 44e10800.pinmux: 142 pins, size 568

[ 1.262375] pinctrl-single 44e10800.pinmux: pin PIN100 already requested by ocp:P9_31_pinmux; cannot claim for 481a0000.spi

[ 1.273762] pinctrl-single 44e10800.pinmux: pin-100 (481a0000.spi) status -22

[ 1.280975] pinctrl-single 44e10800.pinmux: could not request pin 100 (PIN100) from group spi1_pins_s0 on device pinctrl-single

so the pin can't be reassigned for use as spi1. Currently trying to figure out what is assigning PIN100 (P9_31_pinmux) and seeing what can be done.

I thought that the new or call dt file would over right any previous settings, but It does look like it.

Regards,

Yendor

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Feb 6, 2021, 5:03:14 PM2/6/21

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Digging down, it looks like 'am335x-bonegreen-wireless-uboot-univ.dts' is been loaded as the default and this includes 'am335x-bonegreen-wireless-common-univ.dtsi'
which in turn sets 'MCASP0_ACLKX' and 'MCASP0_FSX' as 'audio' on the P9 header.

Question is it possible to modify 'am335x-bonegreen-wireless-uboot-univ.dts' to allow me to use SPI1 on the pins I want?

The pins I need are:

ZCZ Ball Pin Name Signal Mode Assumed Commands

A13 MCASP0_ACLKX SPI1_SCLK 3 AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3)

B13 MCASP0_FSX SPI1_D0 3 AM33XX_IOPAD(0x0994, PIN_INPUT_PULLUP | INPUT_EN | MUX_MODE3)

D12 MCASP0_AXR0 SPI1_D1 3 AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3)

V17 GPMC_A11 LoRa_CS1 7 AM33XX_IOPAD(0x086c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7)

Is anyone able to show me what would need to be modified, Thanks.

Robert Nelson

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Feb 6, 2021, 8:03:03 PM2/6/21

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On Sat, Feb 6, 2021 at 4:03 PM Yendor <rodney....@gmail.com> wrote:
>
> Digging down, it looks like 'am335x-bonegreen-wireless-uboot-univ.dts' is been loaded as the default and this includes 'am335x-bonegreen-wireless-common-univ.dtsi'
> which in turn sets 'MCASP0_ACLKX' and 'MCASP0_FSX' as 'audio' on the P9 header.
>
> Question is it possible to modify 'am335x-bonegreen-wireless-uboot-univ.dts' to allow me to use SPI1 on the pins I want?
>
> The pins I need are:
> ZCZ Ball Pin Name Signal Mode Assumed Commands
> A13 MCASP0_ACLKX SPI1_SCLK 3 AM33XX_IOPAD(0x0990, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3)
> B13 MCASP0_FSX SPI1_D0 3 AM33XX_IOPAD(0x0994, PIN_INPUT_PULLUP | INPUT_EN | MUX_MODE3)
> D12 MCASP0_AXR0 SPI1_D1 3 AM33XX_IOPAD(0x0998, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE3)
> V17 GPMC_A11 LoRa_CS1 7 AM33XX_IOPAD(0x086c, PIN_OUTPUT_PULLUP | INPUT_EN | MUX_MODE7)
>
> Is anyone able to show me what would need to be modified, Thanks.
>

That's right, the BBGW, has the audio muxed to the wl18xx's
bluetooth.. The idea was to stream bluetooth audio.. i don't think
this is fully supported yet either.. (aka there was a random
driver/bugs..)

Regards,

--
Robert Nelson
https://rcn-ee.com/

Yendor

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Feb 6, 2021, 8:22:36 PM2/6/21

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Thanks for the info Robert, would you know how I could reclaim / rewrite these pins to act as SPI pins?

What would be the best way of doing this? modify 'am335x-bonegreen-wireless-uboot-univ.dts' or can we get the boards to load a custom default dt config?

Regards,

Robert Nelson

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Feb 7, 2021, 10:39:02 AM2/7/21

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On Sat, Feb 6, 2021 at 7:22 PM Yendor <rodney....@gmail.com> wrote:
>
> Thanks for the info Robert, would you know how I could reclaim / rewrite these pins to act as SPI pins?
>
> What would be the best way of doing this? modify 'am335x-bonegreen-wireless-uboot-univ.dts' or can we get the boards to load a custom default dt config?

Honestly, since you have a custom board, i'd just start carving a new
*.dtb and stop using overlays for other boards..

Yendor

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Feb 7, 2021, 2:27:47 PM2/7/21

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Hi Robert,

Been completely new to all this what would be the best why to begin writing a new *.dtb

Regards,

jonnymo

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Feb 8, 2021, 5:09:38 PM2/8/21

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Actually, Bootlin has a Device Tree 101 Webinar scheduled for tomorrow. You might find this useful:

https://www.eventbrite.fr/e/webinar-device-tree-101-registration-135964923747?utm_source=eventbrite&utm_medium=email&utm_campaign=event_reminder&utm_term=eventname

They have some free documentation on their site as well.:

https://bootlin.com/

This is on the Beagleboard page:

https://beagleboard.org/blog/2018-01-17-building-a-device-tree-overlay-for-your-new-pocketcape-design

For the Beaglebone specific stuff, the Derek Molloy book is quite handy. The Second Edition is more relevant to the current kernel implementation.

https://www.amazon.com/Exploring-BeagleBone-Techniques-Building-Embedded-dp-1119533163/dp/1119533163/ref=dp_ob_title_bk

There is a ton of info out there, so others may have their own references.

Cheers,

Jon

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Yendor

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Feb 12, 2021, 4:08:55 PM2/12/21

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Thanks Jon for the links,

Looking at the Beagleboard blog:

https://beagleboard.org/blog/2018-01-17-building-a-device-tree-overlay-for-your-new-pocketcape-design

I got the Idea that maybe all I need to do is free up some pins, so trawling through https://github.com/beagleboard/bb.org-overlays/blob/master/src/arm, I found BB-SPIDEV1-00A0.dts so using that as my base I came up with the below changing to use my pins.

/*

* Virtual cape for LoRa mPCIe on connector pins P8.19 P9.23 P9.29 P9.30 P9.31 P2.02

*/

/dts-v1/;

/plugin/;

#include <dt-bindings/board/am335x-bbw-bbb-base.h>

#include <dt-bindings/pinctrl/am33xx.h>

/ {

compatible = "ti,beaglebone", "ti,beaglebone-black", "ti,beaglebone-green";

/* identification */

part-number = "SEEED_SENSECAP_GATEWAY";

version = "00A0";

/* state the resources this cape uses */

exclusive-use =

/* the pin header uses */

"P8.19", /* LoRa Power */

"P9.23", /* LoRa Reset */

"P9.29", /* LoRa SPI1_D0 */

"P9.30", /* LoRa SPI1_D1 */

"P9.31", /* LoRa SPI1_SCLK */

"P2.02", /* LoRa CS1 */

/* the hardware ip uses */

"spi1";

/*

* Helper to show loaded overlays under: /proc/device-tree/chosen/overlays/

*/

fragment@0 {

target-path="/";

__overlay__ {

chosen {

overlays {

SEEED_SENSECAP_GATEWAY-00A0 = __TIMESTAMP__;

};

/*

* Free up the pins used by the cape from the pinmux helpers.

*/

fragment@1 {

target = <&ocp>;

__overlay__ {

P8_19_pinmux { status = "disabled"; }; /* LoRa Power */

P9_23_pinmux { status = "disabled"; }; /* LoRa Reset */

P9_29_pinmux { status = "disabled"; }; /* LoRa SPI1_D0 */

P9_30_pinmux { status = "disabled"; }; /* LoRa SPI1_D1 */

P9_31_pinmux { status = "disabled"; }; /* LoRa SPI1_SCLK */

P2_02_pinmux { status = "disabled"; }; /* Lora CS1 */

};

fragment@2 {

target = <&am33xx_pinmux>;

__overlay__ {

/* default state has all gpios released and mode set to uart1 */

spi1_pins_s0: spi1_pins_s0 {

pinctrl-single,pins = <

0x190 0x33 /* mcasp0_aclkx.spi1_sclk, INPUT_PULLUP | MODE3 */

0x194 0x33 /* mcasp0_fsx.spi1_d0, INPUT_PULLUP | MODE3 */

0x198 0x13 /* mcasp0_axr0.spi1_d1, OUTPUT_PULLUP | MODE3 */

0x6c 0x17 /* gpmc_a11.gpio1_27, OUTPUT_PULLUP | MODE7 */

>;

};

fragment@3 {

target = <&spi1>;

__overlay__ {

#address-cells = <1>;

#size-cells = <0>;

status = "okay";

pinctrl-names = "default";

pinctrl-0 = <&spi1_pins_s0>;

ti,pio-mode; /* disable dma when used as an overlay, dma gets stuck at 160 bits... */

channel@0 {

#address-cells = <1>;

#size-cells = <0>;

compatible = "spidev";

symlink = "spi/1.0";

reg = <0>;

spi-max-frequency = <16000000>;

};

channel@1 {

#address-cells = <1>;

#size-cells = <0>;

compatible = "spidev";

symlink = "spi/1.1";

reg = <1>;

spi-max-frequency = <16000000>;

};

This been the first go, this does not compile as I get an syntax error 'Error: SEEED_SENSECAP_GATEWAY-00A0.dts:8.1-9 syntax error'

While I work through this, I just want to ask will this approach work?

Welcome any help or pointers.

Kind Regards,

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