On Mon, 17 Jun 2019 05:44:09 -0700 (PDT),
hamidkav...@gmail.com declaimed the
following:
>
>I want to send some data to a micro controller with a beaglebone black
>(beagle bone is master). As shown in the picture, the delay between falling
>edge of cs and first rising edge of clock is too much. could you please
>tell me how to decrease it? the image is taken from a logic analyzer which
>its sampling rate is lower than SPI bitrate.
>
Why does it matter? Chip Select serves to "wake up" the target chip,
making it ready to respond to the clock changes. Some targets may need the
time to activate circuits. Data transfer is done on the clock transitions.
A circuit with a single target could, in theory, have the CS line tied
permanently using a pull-up/pull-down resistor (since you state a falling
edge, I'd guess pull-down to ground would be the permanent mode).
--
Wulfraed Dennis Lee Bieber AF6VN
wlf...@ix.netcom.com http://wlfraed.microdiversity.freeddns.org/