Maybe some code in the post will promote some response:
Main Application:
#include <stdio.h>
#include <pruss_intc_mapping.h>
#include <prussdrv.h>
#include <poll.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h>
#define DEVICE_NAME "/dev/rpmsg_pru30"
int main(int argc, char* argv[])
{
int result = 0;
struct pollfd pollfds[1];
pollfds[0].fd = open(DEVICE_NAME, O_RDWR);
if (pollfds[0].fd < 0) {
printf("Failed to open %s\n", DEVICE_NAME);
return -1;
}
/* Send 'hello world!' to the PRU through the RPMsg channel */
result = write(pollfds[0].fd, "hello world!", 13);
while (1) {
prussdrv_pru_wait_event(PRU_EVTOUT_0);
printf("Responding to interrupt\n");
prussdrv_pru_clear_event(PRU_EVTOUT_0, PRU0_ARM_INTERRUPT);
}
return 0;
}
PRU Code:
#include <stdint.h>
#include <pru_cfg.h>
#include <pru_intc.h>
#include "resource_table_empty.h"
volatile register uint32_t __R30;
volatile register uint32_t __R31;
#define PRU_ARM_INTERRUPT 19
#define HOST_NUM 2
#define CHAN_NUM 2
#define PRU_ARM_INTERRUPT_PULSE 0x23
#define HOST_INT ((uint32_t) 1 << 31)
// PRU Interrupt control registers
#define PRU_INTC 0x00020000
// Start of PRU INTC registers TRM 4.3.1.2
#define PRU_INTC_GER ((volatile uint32_t *)(PRU_INTC + 0x10))
// Global Interrupt Enable, TRM 4.5.3.3
#define PRU_INTC_SICR ((volatile uint32_t *)(PRU_INTC + 0x24))
// Interrupt, TRM 4.5.3.6
#define PRU_INTC_GPIR ((volatile uint32_t *)(PRU_INTC + 0x80))
// Interrupt, TRM 4.5.3.11
void main(void)
{
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
// Globally enable host interrupts
CT_INTC.GER = 0x1;
/* Clear any pending PRU-generated events */
__R31 = 0x00000000;
/* Enable Host interrupt 2 */
CT_INTC.HIEISR |= HOST_NUM;
//Enable the system event to be propagated through the INTC
CT_INTC.EISR |= PRU_ARM_INTERRUPT;
/* Map channel 2 to host 2 */
CT_INTC.HMR0_bit.HINT_MAP_2 = CHAN_NUM;
/* Map PRU0_ARM_INTERRUPT (event 19) to channel 2 */
CT_INTC.CMR4_bit.CH_MAP_19 = CHAN_NUM;
/* Ensure PRU_ARM_INTERRUPT is cleared */
CT_INTC.SICR = PRU_ARM_INTERRUPT;
volatile uint32_t gpio;
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
gpio = 0x000F;
while (!(__R31 & HOST_INT)) {
}
while (1) {
__R30 ^= gpio;
__delay_cycles(1000000000);
__R31 = PRU_ARM_INTERRUPT_PULSE;
// Clear interrupt
CT_INTC.SICR = 15;