You can only do no-jitter bit-banging if you use the PRU direct
outputs, and those are unique to each PRU core so there is no
possibility for contention between the PRU cores for access.
Any access to the standard GPIO registers will always have some
jitter, as the write transactions from the PRU have to cross the
on-chip interconnect fabric and transition to a separate clock domain.
That said, the jitter is typically very low (5-10 nS) and is unlikely
to be a significant problem. The very significant jitter seen when
accessing the GPIO registers with the ARM core is related more to task
scheduling and operating system effects than the low-level bus
transactions to the GIPO registers, and does not exist on the PRUs.
On 1/9/2019 3:06 AM, ithinu wrote:
> So it means that I can do no-jitter bit banging if only one PRU accesses
> the GPIO, and if the unit does not use any shared resources? That would be
> great.
>
> On Tuesday, January 8, 2019 at 10:43:36 PM UTC+1, Charles Steinkuehler
> wrote:
>>
>> The PRUs are mostly deterministic when accessing resources within the
>> local PRU-ICSS block. The "mostly" comes from potential contentions
>> if you have both PRU cores accessing the same resource (eg: PRU0 and
>> PRU1 both trying to access the local UART) in which case one of the
>> PRU cores will stall briefly.
>>
>> The PRUs are less deterministic when accessing resources outside the
>> PRI-ICSS block (eg: SDRAM or GPIO registers) where the transaction is
>> subject to synchronization delays, bus congestion on the L3/L4
>> interconnect, etc.
>>
>>
cha...@steinkuehler.net <javascript:>
>>
>
--
Charles Steinkuehler
cha...@steinkuehler.net