CAN interfaces have incorrect bitrate

[jsampson]

I am trying to get the Swiftnav Piksi Multi eval board to output CAN data. If I initialize both interfaces on the board using:

ip link set can0 type can bitrate 200000

ip link set can1 type can bitrate 200000

ip link set can0 up

ip link set can1 up

candump can0

cansend can1 5A1#11.22.33.44.55.66.77.88  - or - cangen can1

This works. But I can't talk to other devices that we use.

I put a scope on it and it appears that the bitrate is 1/5 of what it should be. If I want a bitrate of 250000 and I put in 1250000, then it looks approximately right on the scope.

I tracked it down to:

./buildroot/output/build/linux-xilinx-v2016.4/Documentation/devicetree/bindings/clock/clock-bindings.txt
./buildroot/output/build/linux-xilinx-v2016.4/Documentation/devicetree/bindings/net/can/xilinx_can.txt

Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings

---------------------------------------------------------

Required properties:
- compatible        : Should be "xlnx,zynq-can-1.0" for Zynq CAN
              controllers and "xlnx,axi-can-1.00.a" for Axi CAN
              controllers and "xlnx,axi-canfd-1.0" for Axi CANFD
              controllers.
- reg            : Physical base address and size of the Axi CAN/Zynq
              CANPS/Axi CANFD registers map.
- interrupts        : Property with a value describing the interrupt
              number.
- interrupt-parent    : Must be core interrupt controller
- clock-names        : List of input clock names - "can_clk", "pclk"
              (For CANPS), "can_clk" , "s_axi_aclk"(For AXI CAN/
              AXI CANFD)
              (See clock bindings for details).
- clocks        : Clock phandles (see clock bindings for details).
- tx-fifo-depth        : Can Tx fifo depth.
- rx-fifo-depth        : Can Rx fifo depth.


Example:

For Zynq CANPS Dts file:
    zynq_can_0: can@e0008000 {
            compatible = "xlnx,zynq-can-1.0";
            clocks = <&clkc 19>, <&clkc 36>;
            clock-names = "can_clk", "pclk";
            reg = <0xe0008000 0x1000>;
            interrupts = <0 28 4>;
            interrupt-parent = <&intc>;
            tx-fifo-depth = <0x40>;
            rx-fifo-depth = <0x40>;
        };
For Axi CAN Dts file:
    axi_can_0: axi-can@40000000 {
            compatible = "xlnx,axi-can-1.00.a";
            clocks = <&clkc 0>, <&clkc 1>;
            clock-names = "can_clk","s_axi_aclk" ;
            reg = <0x40000000 0x10000>;
            interrupt-parent = <&intc>;
            interrupts = <0 59 1>;
            tx-fifo-depth = <0x40>;
            rx-fifo-depth = <0x40>;
        };

For Axi CANFD Dts file:
    canfd_0: canfd@43c00000 {
            compatible = "xlnx,canfd-1.0";
            clocks = <&clkc 0 &clkc 1>;
            clock-names = "can_clk", "s_axi_aclk";
            reg = <0x43c00000 0x10000>;
            interrupt-parent = <&intc>;
            interrupts = <0 31 4>;
            tx-fifo-depth = <8>;
            rx-fifo-depth = <8>;
        };

But I don't what to do from here. I don't knpow if this is ARM or FPGA or something else...

Can anybody point me in the right direction?

Jeff Sampson

Danfoss Power Solutions

[jsampson]

On Wednesday, May 9, 2018 at 11:07:41 AM UTC-5, jsampson wrote:

I put a scope on it and it appears that the bitrate is 1/5 of what it should be. If I want a bitrate of 250000 and I put in 1250000, then it looks approximately right on the scope.

It wasn't consistently talking to other devices. I looked at it harder on a scope. It is not a factor of 5, it is a factor of 4.8. So I have to specify a bitrate of 1200000 (instead of 1250000) to get it to run at 250000 bits/sec and talk to devices from the real world. Then I get the expected 4us per bit.