Hi,
This is a discussion group for the Xbitmanip extension for RISC-V. The goal is to create a draft for a bit-manipulation ISA extension, and implement this draft in multiple cores, and add compiler support, and then donate this draft to the RISC-V Foundation as a starting point for a new task group for a standard bit manipulation extension. The draft we are working on is based on the work of the original bit manipulation task group that was dissolved in November 2017.
Afaict the next steps are:
(1) clarify the legal status of the last draft produced by the original bit manipulation task group,
(2) researching prior art for the instructions, where insufficient information is provided in the draft spec,
(3) creating efficient C code snippets and idiomatic compressed and uncompressed assembler codes for common bit manipulation operations that aren't directly supported as instructions by Xbitmanip, and
(4) allocate instruction encodings in the custom instruction space to be used by our implementations.
From what I've seen so far (3) would answer most FAQs. It would also provide patterns for macro-op fusion for cores that want to add direct HW support for those operations.
The PULP group at ETH Zurich has published about PULP. The bit manip instructions currently in PULP have a large overlap with the instructions in the bitmanip draft afair, so maybe they also have already some literature research that could help with prior art? We might also be able to leverage some of their existing compiler work.
I'd be happy to organize the effort, i.e. garden the wiki, remind people of their commitments, and schedule the occasional zoom conference call.
If you'd be interested in being a part of this effort, then please subscribe to the riscv-xbitmanip google group (mailing list):
https://groups.google.com/forum/#!forum/riscv-xbitmanip
regards,
- clifford