PSCI for H3

[wens Tsai]

Hi everyone,

I got my Orange Pi PC booting U-boot now, using Hans' sunxi-wip branch that
includes Jens' patches.

For PSCI and SMP, it seems the H3 follows the structure of previous sun8i SoCs.
The CPUCFG registers line up. The manual doesn't have the PRCM, so I'll have to
dig through the SDK.

One other thing is the SMTA, or Secure Memory Touch Arbiter, which we last
encountered issues with on the A31s. This controls non-secure access to a whole
bunch of peripherals, which we'll need to enable for Linux to run non-secure.

Anyway, this is just a preliminary evaluation of the work needed for PSCI.
Nothing has actually been done or tested.


Regards
ChenYu

[Chen-Yu Tsai]

Hi everyone,

(Resent with my correct email address...)

[Jens Kuske]

On 16/11/15 07:26, Chen-Yu Tsai wrote:
> Hi everyone,

>
> I got my Orange Pi PC booting U-boot now, using Hans' sunxi-wip branch that
> includes Jens' patches.
>
> For PSCI and SMP, it seems the H3 follows the structure of previous sun8i SoCs.
> The CPUCFG registers line up. The manual doesn't have the PRCM, so I'll have to
> dig through the SDK.
>
> One other thing is the SMTA, or Secure Memory Touch Arbiter, which we last
> encountered issues with on the A31s. This controls non-secure access to a whole
> bunch of peripherals, which we'll need to enable for Linux to run non-secure.

There is also register 0x2f0 in the CCU, it defaults to disabling
non-secure access to all clock registers.

Jens

[Siarhei Siamashka]

How about just enabling SMP on Allwinner H3 in an old unfashionable way
while all these non-secure access limiters are still being under
investigation?



diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 0faa38a..d23ed84 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -51,6 +51,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "allwinner,sun6i-a31";

cpu@0 {
compatible = "arm,cortex-a7";
@@ -591,5 +592,15 @@
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ prcm@01f01400 {
+ compatible = "allwinner,sun8i-h3-prcm";
+ reg = <0x01f01400 0x200>;
+ };
+
+ cpucfg@01f01c00 {
+ compatible = "allwinner,sun8i-h3-cpuconfig";
+ reg = <0x01f01c00 0x300>;
+ };
};
};
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index e8483ec..8ca4064 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -44,6 +44,9 @@ static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
struct device_node *node;

node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm");
+ if (!node)
+ node = of_find_compatible_node(NULL, NULL,
+ "allwinner,sun8i-h3-prcm");
if (!node) {
pr_err("Missing A31 PRCM node in the device tree\n");
return;
@@ -57,6 +60,9 @@ static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)

node = of_find_compatible_node(NULL, NULL,
"allwinner,sun6i-a31-cpuconfig");
+ if (!node)
+ node = of_find_compatible_node(NULL, NULL,
+ "allwinner,sun8i-h3-cpuconfig");
if (!node) {
pr_err("Missing A31 CPU config node in the device tree\n");
return;
--
2.4.10


--
Best regards,
Siarhei Siamashka

[Chen-Yu Tsai]

On Wed, Dec 23, 2015 at 6:14 PM, Siarhei Siamashka
<siarhei....@gmail.com> wrote:
> On Tue, 17 Nov 2015 15:32:30 +0100
> Jens Kuske <jens...@gmail.com> wrote:
>
>> On 16/11/15 07:26, Chen-Yu Tsai wrote:
>> > Hi everyone,
>> >
>> > I got my Orange Pi PC booting U-boot now, using Hans' sunxi-wip branch that
>> > includes Jens' patches.
>> >
>> > For PSCI and SMP, it seems the H3 follows the structure of previous sun8i SoCs.
>> > The CPUCFG registers line up. The manual doesn't have the PRCM, so I'll have to
>> > dig through the SDK.
>> >
>> > One other thing is the SMTA, or Secure Memory Touch Arbiter, which we last
>> > encountered issues with on the A31s. This controls non-secure access to a whole
>> > bunch of peripherals, which we'll need to enable for Linux to run non-secure.
>>
>> There is also register 0x2f0 in the CCU, it defaults to disabling
>> non-secure access to all clock registers.
>>
>> Jens
>>
>
> How about just enabling SMP on Allwinner H3 in an old unfashionable way
> while all these non-secure access limiters are still being under
> investigation?

I'm not against it, though I was considering removing the SMP code.

BTW, without docs on the PRCM, do we know if the H3 has the same power clamps
as the A31? FYI the A23 SMP code is the same as A31, just without the power
clamps.

Thanks
ChenYu

[Siarhei Siamashka]

Yes. I inspected the kernel sources from the Allwinner SDK and it looks
like A31 and H3 are taking exactly the same code path (using the same
ifdef guards everywhere):
https://github.com/allwinner-zh/linux-3.4-sunxi/blob/55599b8209bb7150140e4d45ef460dbff6c876dd/arch/arm/mach-sunxi/include/mach/sun8i/platsmp.h#L124-L139

"SUN8IW1 = A31" and "SUN8IW7 = H3" according to
http://linux-sunxi.org/Allwinner_SoC_Family#2013_naming_scheme_change


I'll also try to see if I can get PSCI working on H3, but it seems to
be a real PITA to debug. Also some parts of the H3 documentation are
missing (PRCM is a good example) and if there happens to be an
undocumented configuration knob responsible to allowing non-secure
access to some important resource, then we hit a brick wall...

[Maxime Ripard]

On Wed, Dec 23, 2015 at 12:14:15PM +0200, Siarhei Siamashka wrote:
> On Tue, 17 Nov 2015 15:32:30 +0100
> Jens Kuske <jens...@gmail.com> wrote:
>
> > On 16/11/15 07:26, Chen-Yu Tsai wrote:
> > > Hi everyone,
> > >
> > > I got my Orange Pi PC booting U-boot now, using Hans' sunxi-wip branch that
> > > includes Jens' patches.
> > >
> > > For PSCI and SMP, it seems the H3 follows the structure of previous sun8i SoCs.
> > > The CPUCFG registers line up. The manual doesn't have the PRCM, so I'll have to
> > > dig through the SDK.
> > >
> > > One other thing is the SMTA, or Secure Memory Touch Arbiter, which we last
> > > encountered issues with on the A31s. This controls non-secure access to a whole
> > > bunch of peripherals, which we'll need to enable for Linux to run non-secure.
> >
> > There is also register 0x2f0 in the CCU, it defaults to disabling
> > non-secure access to all clock registers.
> >
> > Jens
> >
>
> How about just enabling SMP on Allwinner H3 in an old unfashionable way
> while all these non-secure access limiters are still being under
> investigation?

I'd really prefer not to.

This ends up being dead code that no-one uses, but we can't really
remove. Adding support for the H3 support would only delay that
removal once again.

What controller are you having issues accessing?

Thanks,
Maxime

--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[Chen-Yu Tsai]

So I finished H3 PSCI support. For the moment everything seems to
work. Though given the limited number of peripherals supported and
used, that may not be complete.

For now the patches are available at

https://github.com/wens/u-boot-sunxi/tree/h3-psci

I'll find some time to post them.


Regards
ChenYu