The HL2 provides a oscillator output via the unpopulated CL2 on the front of the board. See page 4/7 with title "Clock" in the schematic. You can add an SMA connector and create a second clock with the low jitter Versa5 clock generator. The source oscillator for the Versa5 is 38.4 MHz, <= 1ppm. This is what Claudio used. Quisk has code to set the oscillator. See VersaOut2 in hermes/quisk_hardware.py.
def VersaOut2(self, divisor): # Use the VersaClock output 2 with a floating point divisor
div = int(divisor * 2**24 + 0.1)
intgr = div >> 24
frac = (div & 0xFFFFFF) << 2
self.WriteVersa5(0x62,0x3b) # Clock2 CMOS1 output, 3.3V
self.WriteVersa5(0x2c,0x00) # Disable aux output on clock 1
self.WriteVersa5(0x31,0x81) # Use divider for clock2
# Integer portion
self.WriteVersa5(0x3d, intgr >> 4)
self.WriteVersa5(0x3e, intgr << 4)
# Fractional portion
self.WriteVersa5(0x32,frac >> 24) # [29:22]
self.WriteVersa5(0x33,frac >> 16) # [21:14]
self.WriteVersa5(0x34,frac >> 8) # [13:6]
self.WriteVersa5(0x35,(frac & 0xFF)<<2) # [5:0] and disable ss
self.WriteVersa5(0x63,0x01) # Enable clock2
# Thanks to Steve Haynal for VersaClock code:
def WriteVersa5(self,addr,data):
data = data & 0x0ff
addr = addr & 0x0ff
## i2caddr is 7 bits, no read write
## Bit 8 is set to indicate stop to HL2
## i2caddr = 0x80 | (0xd4 >> 1) ## ea
self.pc2hermeslitewritequeue[0:5] = 0x7c,0x06,0xea,addr,data
self.WriteQueue(1)
def EnableCL2_sync76p8MHz(self):
self.WriteVersa5(0x62,0x3b) ## Clock2 CMOS1 output, 3.3V
self.WriteVersa5(0x2c,0x01) ## Enable aux output on clock 1
self.WriteVersa5(0x31,0x0c) ## Use clock1 aux output as input for clock2
self.WriteVersa5(0x63,0x01) ## Enable clock2
def EnableCL2_61p44MHz(self):
self.WriteVersa5(0x62,0x3b) ## Clock2 CMOS1 output, 3.3V
self.WriteVersa5(0x2c,0x00) ## Disable aux output on clock 1
self.WriteVersa5(0x31,0x81) ## Use divider for clock2
## VCO multiplier is shared for all outputs, set to 68 by firmware
## VCO = 38.4*68 = 2611.2 MHz
## There is a hardwired divide by 2 in the Versa 5 at the VCO output
## VCO to Dividers = 2611.2 MHZ/2 = 1305.6
## Target frequency of 61.44 requires dividers of 1305.6/61.44 = 21.25
## Frational dividers are supported
## Set integer portion of divider 21 = 0x15, 12 bits split across 2 registers
self.WriteVersa5(0x3d,0x01)
self.WriteVersa5(0x3e,0x50)
## Set fractional portion, 30 bits, 2**24 * .25 = 0x400000
self.WriteVersa5(0x32,0x01) ## [29:22]
self.WriteVersa5(0x33,0x00) ## [21:14]
self.WriteVersa5(0x34,0x00) ## [13:6]
self.WriteVersa5(0x35,0x00) ## [5:0] and disable ss
self.WriteVersa5(0x63,0x01) ## Enable clock2