FPGA Bit Files for Testing and Big Lead on Rob's Problem

[Steve Haynal]

Hello List,

I have added 3 compiled bit files to github to facilitate testing, including 1 test that only requires a BeMicro SDK. Source code and a better description will come later. The good news is I was able to duplicate the problem Rob sees on his builds on my prototype and know what the problem is. On power up, the FPGA sometimes locks on at 2x or 1/2x the frequency of the AD9866 clock, or the AD9866 is generating 2x or 1/2x the specified frequency. When 2x occurs, you see the problem Rob has seen with low gain. When 1/2x occurs, you see the garbled audio that I sometimes see. There are probably settings with a PLL that can make this frequency lock more consistent but more investigation for a fix is needed. 

The tests are in rtl/bitfiles and described below.

Hermes_Lite_NoAD9866
This test does not require a Hermes-Lite board, just a BeMicro SDK, and I would appreciate reports from people on how it works. It implements a single Hermes receiver/transmitter but the receiver is fed a sine wave at 4.607 MHz. You can connect to this with any Hermes software and see a strong signal at 4.607 MHz. It is interesting to see how various software and the FPGA processing produce artifacts with no real input. If someone has an inclination for analysis, this would be an interesting setup to analyze. You can vary the input and see/measure any distortion or noise through the entire chain. You can program the bit file on your BeMicro SDK with the standard Altera Quartus programmer. Once programmed, you can use the HPSDRProgrammer_v2_nopcap to write the firmware. It requires that you connect it to a network with a DHCP server to obtain the IP address. All the bit files use a fixed MAC address of  {8'h00,8'h1c,8'hc0,8'ha2,8'h22,8'h5c}.

The 8 LEDs on the BeMicroSDK in this test are:
LED0 FPGA_PTT
LED1 Receiving any ethernet traffic
LED2 Receiving ethernet traffic for this MAC
LED3 Sending ethernet traffic
LED4 Synced
LED5 Hermes_atten bit 4 (move the attenuator slider to see this change)
LED6 Hermes_atten bit 3
LED7 Heatbeat, turns on every 0.85 seconds, pretty much every second.


Hermes_Lite_Test
This test implements a single receiver/transmitter with a fixed gain of +20 dB. The LEDs are as follows:

LED[0:1] ADCp and ADCn clips. Use this to check the balance of input signals.
LED[2:6] DAC level. Use this to see if a signal is being sent to the DAC.
LED[7] Heartbeat, turns on every 0.85 seconds.

The first time I turned on this test, the heartbeat was twice as fast and I saw the same problems Rob sees.

Hermes_Lite
This is the stock 2 receiver build. It was built with Quartus 14.01 using the latest code in github. I tested it on my prototype.


73,

Steve
KF7O

[Steve Haynal]

Over lunch I updated the github bit files (Hermes_Lite/rtl/bitfiles) to implement some ideas to address the clock startup issue that Rob has seen. Rob - can you test this bitfile? It is standard 2 RX but includes the 0.85 second heartbeat LED. Check the MD5SUM to make sure you grab the recent version.

md5sum Hermes_Lite_09SDK.*

048cff9094373fb1df80683c95c5cd72  Hermes_Lite_09SDK.sof

5ca6f6733f6d140fb813182420a3ca37  Hermes_Lite_09SDK.rbf

73,

Steve

KF7O

[joe]

Steve,

I loaded the Hermes-lite-NoAD9866 .sof file to my Altera board (I think) and I can see s signal at 4.06MHZ using PowerSDR however as a complete novice I would like to comment
on a few problems.

The LED's on my board start the count from 1 not 0 all the functions work such as PTT and the attenuator just moved one count up the heartbeat shows on LED 8.

I don't know how the setup Hermes-lite using power SDR. I see Hermes listed but no hermes-lite  as I use the normal Hermes selection I have no audio as the Hermes board must have it's audio output on board.

You and Rob are light years ahead of me and it it wasn't for Sid's help I wouldn't have gotten this far.

Joe    wa9cgz      near Chicago

[Steve Haynal]

Hi Joe,

That is great that you were able to load the test .sof file and see the signal at 4.06 MHz using PowerSDR. I would like to gather information before finalizing the next revision on how stable the ethernet interface and firmware is on multiple BeMicro SDKs. It would be useful if you did the following 10 times and let me know how many times out of 10 things came up okay:

1. Power down the BeMicro SDK completely and wait for 20 seconds
2. Power it back up
3. Program with the SOF (skip this step if you have written the EEPROM with the HPSDRProgramming software)
4. Connect with PowerSDR and verify that the signal is there

The post about the LEDs was off the top of my head and I apologize for being one off on the LED numbering. In general, documentation is lacking. We should setup a place or wiki where others can write and add to the documentation. Any suggestions or volunteers? What about the wiki pages on a github project?

For now, you can only select Hermes in PowerSDR. This provides basic compatibility but there will have to be software updates to take full advantage and make it easiest to use a Hermes-Lite. It would also be interesting if you can bring up the Hermes-Lite with other Hermes software like cuSDR, KISS console, GNU Radio, etc. I think there is a list of Hermes compatible software on the Hermes site.

With PowerSDR, you can use a virtual audio cable. I use the VB-Audio cable as it is donationware but there are others. If you google PowerSDR and virtual audio cable or vac, you'll find helpful information. For example,  http://kc.flex-radio.com/KnowledgebaseArticle50362.aspx

73,

Steve

KF7O

[joe]

Steve,

I loaded the code several times so far so good. I was able to use the VAC as you suggested and now have audio.

Now the hard part could you or someone show me how to load the .sof file into the eeprom or to a SD card so each time the ALTERA is powered up it will load and I don't
need to reprogram it keep in mind that I'm a novice with the FPGA.

Thanks   joe   wa9cgz

[Rob Frohne]

Hi Joe,

Download the HPSDRProgrammer_v2_nopcap.  Then you can use it to discover the hermes-lite and program it.  I just tried it and it works for me.

73,

Rob
KL7NA

--
You received this message because you are subscribed to the Google Groups "Hermes-Lite" group.
To unsubscribe from this group and stop receiving emails from it, send an email to hermes-lite...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

[Rob Frohne]

Hi Joe,

This may not have been as clear as I would like.  What I was trying to do was answer your question about how to make the firmware non-volitile.

73,

Rob
KL7NA

[Rob Frohne]

Hi Joe,

In case this might be a problem  for you, you need to install the pcap libraries as mentioned here.  I had them already installed.

73,

Rob
KL7NA

[Steve Haynal]

Hi Joe,

As Rob mentioned, you will need to install the HPSDRProgrammer_v2 from the Hermes site. There are versions for both Windows and Linux. There are better instructions on the Hermes site on how to get that software running and use it. Once you have it working, discovery and FPGA firmware programming should work as expected. Once the firmware is programmed to eeprom, I always update via HPSDRProgrammer and only use the BeMicro's USB blaster if something breaks.

You can not program a static IP or MAC address with HPSDRProgrammer yet though. In the next revision, there will either be a dedicated eeprom for the IP or MAC or this information will be stored in the BeMicro's eeprom, and you will be able to program static IP and MAC via HPSDRProgrammer.

73,

Steve

KF7O

[ik1xpv]

Hello Steve

Many thanks for the project and the support.

I loaded the Hermes_lite_NoAD9866 bitfile and it runs as expected, DHCP

Nevetheless it seems to me that the "testclocks.v" file is not saved in the

Github image. Please add it.

 

I just populated a pcb 1.1 and I'm starting its debugging. Your and Rob support help a lot. 

(It read that the RTCLK must be assigned to PIN_P14 insted of PIN_P11).

73'

Oscar

IK1XPV

[Steve Haynal]

Hello Oscar,

I just pushed the testclocks.v to the public git repository. My local repository is in a state of flux as I am working on the WaveShare interface. I've been trying not to disrupt the main repository, but should probably just branch. I suggest you get a known working v1.1 bit file from Rob to eliminate any compilation issues as you bring up your v1.1 Hermes-Lite. Good luck and please post your bring up experiences to the group.

73,

Steve

KF7O

[Rob Frohne]

Hi Oscar,

Attached are the bitfiles I've been using.  The Hermes_Lite_09SDK-v1.1.rbf has the same MAC address as the v-1.0 units.    The other one, Hermes_Lite_09SDK-v1.1-mac.rbf has the MAC address increased by one.

Glad to see you built up a board.  My procedure  for bringing up a board is:

• Using the Programming Tool in Altera's suite, flash the code for use with no Hermes-Lite as you have done.
• Connect that via Ethernet and use the HPSDRProgrammer (no pcap version on Linux) to program one of the  files I have enclosed here.
• Inspect very carefully under a microscope or magnifier looking for bridges or bad connections.  Look on both sides.
  
• Fix anything bad you find.
  
• Check that your power isn't shorted by a solder bridge or with an ohmmeter.
• Connect power and pray.  Not necessarily in that order. :-) Watch the lights and ammeter on the power supply.
• Watch the lights and ammeter on the power supply.
• If all seems okay, try and ping the board.
• If all seems okay, run hpsdr-server and dspserver and qtradio.

Hope this is a help!

73,

Rob
KL7NA

--
You received this message because you are subscribed to the Google Groups "Hermes-Lite" group.
To unsubscribe from this group and stop receiving emails from it, send an email to hermes-lite...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

-- 
Rob Frohne, PhD, PE
Professor
EF Cross School of Engineering
Walla Walla University
100 SW 4th Street
College Place, WA 99324
(509) 527-2075

[ik1xpv]

Steve and Rob,

many thanks for the support.

I'm a  beginner with Altera and Quartus (14.0) so far I have been able to compile the project I got via github and convert the .sof  file into the .jic file and program the BeMicro SDK flash using Altera programmer.

The Hermes_Lite_NoAD9866_09SDK image has been fine to verify the target operation. It operares with PowerSDR and cuSDR64 using direct cable connection (AIPA) with the PC running Win7 64. The 4.6 MHz reference is there.

I installed the HPSDRProgrammer_2 a version 2.0.4.0  2013-6-9 in Win7. It recognizes the AIPA connected BeMicro board as  Hermes 2.5. Nevertheless I have not been able to load .rbf image using it. The loading fails and the message is power cycle and retry. I used Quartus programmer to recover.

I have not been able to find how to use Quartus programmer to load .rbf files into BeMicro SDK or how to convert from .rbf to .jic.

What is the right way?

I populated the pcb1.1 with all the components and the board power on with a power current in the range 200 mA.  I have not yet the right clock oscillator (73.728 or 61.44), to measure the power consumption I used a 75 MHz clock.

I imagine that a branch image with the pcb1.1 reference configuration would help me in debugging the hardware bugs I made.

Thanks again for your great project, help and support.

Ciao from Italy

Oscar

IK1XPV

[Steve Haynal]

Hello Oscar,

You don't need a .jic file as the serial eeprom is programmed via the HPSDRProgrammer. I use the .sof file to program directly (volatile) via the USB blaster interface using the Quartus prorammer. The .rbf is used to program the serial eeprom via the HPSDRProgrammer. See page 33 in http://www.arrownac.com/offers/altera-corporation/bemicro/BeMicro_Instructions_Embedded_System_Lab.pdf for programming details.

I've never had problems with HPSDRProgrammer but I've always run the Linux version. There is a newer version (July 2014) you can try: http://openhpsdr.org/download.php

You can ask Rob to send .sof files so you can try to program it via the USB Blaster.

You will need to have the correct crystal frequency. It is a multiple of 48kHz and there are data flow rates in the RTL that depend on it being such. You may get buffer overflow/underflows by not using the correct frequency which can keep things from working

73,

Steve

KF7O

[ik1xpv]

Hello Steve and Rob,

Following yours advice I got some life signal from my Hermes Lite !

I tested again HPSDRProgrammer but on my Windows pc I was not able to use it, for the moment I use the Quartus programmer .

I have understood that the clock frequency is critical as it synchronize all the Machine. Nevertheless I have at home only some oscillators and I decided to test with a 80.000 MHz. 

I used the Steve Hermes_Lite_Test configuration. 

I modified the pll using the Altera Wizard, here attached the file. 

I modified the assignment of ad9866_rxclk to PIN_P14 as I use the Rob pcb 1.1.

The receiver operates! Thanks to All.

Here attached some picture with a random wire  antenna.

Possibly I will spend the next months to understand what I have done. Hi.

Ciao

Oscar

[Steve Haynal]

Hello Oscar,

Congratulations on RX and thanks for the pictures. 

The clock from the oscillator goes directly to the AD9866 where it is the clock for the A/D converter. From there, the AD9866 passes it to the FPGA. This is done so that the A/D converter has access to the cleanest and most jitter-free clock as a good clock can be compromised by passing through a FPGA. Low jitter is important for highspeed A/D conversion and you can find many references that explain why. From my understanding of what you have done, the A/D converter is still converting at 80 MHz (since the clock reaches there first) but you've used a PLL to convert the 80 MHz to 73.728 MHz for the FPGA so that data is read from the A/D at the correct rate. I suspect there will be FIFO overflows in the A/D such that you hear crackling, and the SDR software is uncalibrated. Is that the case? 

I shared some measurements in the post Next revision PCB to be submitted Oct 5. These seemed to be fairly consistent across versions 0.9,1.0 and 1.1. Can you repeat these measurements to see if there is any added phase noise due to clock differences with your Hermes-Lite?

What technique did you use to solder the AD9866? Did that include the thermal pad?

It looks like you are powering everything over the USB connector. That is new and interesting to see.

73,

Steve

KF7O

[Rob Frohne]

Congratulations. Oscar! I'm so glad to see your progress.

73,

Rob
KL7NA

--
Sent from my Android device with K-9 Mail. Please excuse my brevity.

[ik1xpv]

Hello Steve,

The clock setup I made is wrong as shown in the S/N results.

I use PowerSDR and Hermes Lite Test configuration with 80 MHz clock patch.

I connected a 50 Ohm load and measure the level in AM with 5 KHz wide filter.

-105 dBm at 1.8 MHz

-115 dBm at 3.5 MHz

-106 dBm at 10 MHz

-126 dBm at 14 MHz

-123 dBm at 21 MHz

-122 dBm at 28 MHz

The clocking must be revised for use of a 80MHz clock...

I have not jet tested the input ferrite transformer I wound over a C6 ferrite core.

I soldered the AD9866 and the pcb by hand using big lens and glasses (I'm 63!). I placed same flux and solder over the thermal pad before soldering the chip side pins.

Then with an air gun I rise the temperature till I saw the chip solder melt and the chip centering itself.

This is not the best way but in my case it seems ok.

I power everything over the USB connector. I use a USB current monitor.

The  mean current I measure is 500mA  (moving from 480 to 510 mA). 

The current of BeMicr SDK with Hermes_Lite_NoAD9866_09SDK.sof without  Hermes Lite  is 180mA.

73,

Oscar

IK1XPV

[Steve Haynal]

Hello Oscar,

Hot air is a perfectly legitimate way to do surface mount. It is good to know that it can be successfully done with the AD9866.

I tried HPSDRProgrammer_v2_nocap on a Windows 7 machine today. I wasn't able to do anything via wireless, but when I had a wired ethernet connection, I was able to detect and program the Hermes-Lite.

Thanks for the PowerSDR measurements. I think we'll have to redo them once you get the proper oscillator. I checked the AD9866 datasheet today and there is a FIFO between the A/D converter and the FPGA inside the AD9866. See page 23. This means the FIFO will overflow as it is being filled at 80 MHz but emptied at 73.728 MHz. This will result in DSP problems.

I think you are just a oscillator away from a functioning Hermes-Lite. I recommend the SiLabs part specified in the BOM as it is fairly low jitter but costs around $5. The Hermes actually uses a ~$20 oscillator. 

73,

Steve 

KF7O

[ik1xpv]

Hello Steve,

Yes, to buy the right clock is better and simpler than to redesign the CIC and FIR chain. HI.

I will repeat the measure with the right clock.

73,

ciao

Oscar

IK1XPV 

[Alan Hopper]

 

Hermes_Lite_NoAD9866
This test does not require a Hermes-Lite board, just a BeMicro SDK, and I would appreciate reports from people on how it works. It implements a single Hermes receiver/transmitter but the receiver is fed a sine wave at 4.607 MHz. You can connect to this with any Hermes software and see a strong signal at 4.607 MHz. It is interesting to see how various software and the FPGA processing produce artifacts with no real input. If someone has an inclination for analysis, this would be an interesting setup to analyze.

 

Steve, 

this intrigued me enough to write a software only Hermes emulator https://github.com/ahopper/Patroclus  so I could see these artifacts.  It might be interesting to compare the fpga output vs my emulator.  I have a bemicroCV and a waveshare board and am waiting for one of your connector boards, once I have it , I'll give it a go.

Alan 

[Steve Haynal]

Hi Alan,

Very interesting work. Thanks for sharing. Is there any DSP (mixing, filtering) of the emulated signal in your software, or is an appropriate "ideal" sine wave directly inserted into the Hermes UDP stream? Your software can help improve both Hermes hardware and software as it can highlight introduced artifacts in either of these links.

Have you shared this with the openHPSDR group? If not, I think you should. It is directly applicable to Hermes, and there is a larger audience on that list.

73,

Steve

KF7O

  

[Alan Hopper]

Steve,

At the moment it is a simple ideal (I hope) sin and cos wave on I and Q data in the udp stream, there is no filtering, if you enter a frequency outside of the bandwidth of the receiver you get a good lesson in aliasing!  It is a bit rough at the moment but seems to work.  Currently changing frequency creates artefacts during the change as phase is messed up. One thought I had was to analyse the returned audio channel from the client to produce some sort of automated goodness factor for sdr clients.  I will post to the openHPSDR group.

Thanks again

Alan

M6NNB