TransWarp III
Stephen Brown
In this article, it says:
>>WHAT 20/28 Mhz 65816? Do you have one?
[cut here]
>last posts about ASIC 65816, they sounded like it's out in samll amount as
>examples, so I assum it's ready for shipment in quantity by now.
I spoke to Tony Fadell of ASIC Enterprises, Inc., last Thursday. In his words,
the chip is "in fab" (fabrication). Production samples apparently only work
to 15 Mhz [ darn :-) ] and he is achieving a good enough yield that they
should be available in any quantity. He also said that he'd be at AppleFest,
ready to sell his chips to anyone (and everyone) who wants.
I will be posting a great deal more info about this chip very soon.
---hey Apple, wanna buy some chips?
UUCP: crash!pro-generic!sb
ARPA: crash!pro-generic!s...@nosc.mil
INET: s...@pro-generic.cts.com
Brian WILLOUGHBY
>In-Reply-To: message from cyl...@eng.umd.edu
>
>In this article, it says:
>>>WHAT 20/28 Mhz 65816? Do you have one?
>[cut here]
>>last posts about ASIC 65816, they sounded like it's out in samll amount as
>>examples, so I assum it's ready for shipment in quantity by now.
>
>I spoke to Tony Fadell of ASIC Enterprises, Inc., last Thursday. In his words,
>the chip is "in fab" (fabrication). Production samples apparently only work
>to 15 Mhz [ darn :-) ] and he is achieving a good enough yield that they
>should be available in any quantity. He also said that he'd be at AppleFest,
>ready to sell his chips to anyone (and everyone) who wants.
I found it hard to believe (and still do) that some college kid has done a
better job all by himself than what the Western Design Center can do with
a team of engineers. Now I'm not too surprised that this "20 MHz" CPU has
turned out to be 15 MHz (which you will note is only about 2 MHz faster
than WDC!).
In addition, WDC rates their processor speed by about 15 different timing
relationships. They rate data and address input and output timing as well
as the relationship between different clock and control signals. If any
ONE of those timing specs does not work at a particular speed, then the
chip is rated at a lower speed. WDC has chips that might run at 20 MHz
(that's a guess on my part) in a custom circuit that is designed to work
around the slower timing ratios. The fact is that the overall CPU speed
is based on many factors, with the slowest measured timing being the limit.
A common misconception about integrated circuits is the assumption that
there are different production runs for each chip speed. Actually, a chip
manufacturer attempts to make every chip at top speed, and then tests the
performance before marking them.
>I will be posting a great deal more info about this chip very soon.
Please do.
>---hey Apple, wanna buy some chips?
I hope they don't, unless they do extensive compatibility testing on them.
At a time when Intel cannot get their own 80486 processors to run 8086
code, I am very suspect of a chip that was designed by a single college
kid.
Don't forget that a 8 MHz 6502 is running like a 35 to 40 MHz 8088
(although I can't say what speed 80486 it can compete with). Also, a
10 MHz 65C816 can keep up with a 20 MHz 68000 (but I wouldn't put it
up against a 68040). This is not considering video or disk I/O.
Brian Willoughby
UUCP: ...!{tikal, sun, uunet, elwood}!microsoft!brianw
InterNet: microsoft!bri...@uunet.UU.NET
or: microsoft!bri...@Sun.COM
Bitnet bri...@microsoft.UUCP
Doug Gwyn
>I found it hard to believe (and still do) that some college kid has done a
>better job all by himself than what the Western Design Center can do with
>a team of engineers.
What "team of engineers"? I thought Mensch and his wife laid out the
65816 design on their kitchen table.
Besides, it's not that hard to design masks for gate arrays.
There is nothing terribly special about the internals of a 65816 CPU,
either. Anybody reasonably competent in digital logic design should
be able to come up with a similar CPU layout if they spent the time.
I don't mean to downplay ASIC's accomplishment, merely to point out
that there is nothing magic about it.
>Now I'm not too surprised that this "20 MHz" CPU has turned out to be 15 MHz
>(which you will note is only about 2 MHz faster than WDC!).
If the ASIC chips are coming out in high yield at 15MHz then they have
done considerably better than WDC, and on the very first shot.
Todd P. Whitesel
>I found it hard to believe (and still do) that some college kid has done a
>better job all by himself than what the Western Design Center can do with
>a team of engineers. Now I'm not too surprised that this "20 MHz" CPU has
>turned out to be 15 MHz (which you will note is only about 2 MHz faster
>than WDC!).
WDC does not have "a team of engineers" -- they have Bill Mensch and his
wife and daughter. The original 65816 mask was laid out BY HAND five
years ago and they have NEVER tried using the state of the art gate array
approach that Tony Fadell had the connections to gain access to.
A couple years ago when I got my hands on the 65816 data sheet I took one
look at the cycle-by-cycle bus state listing (all of two pages) and said
"you know, this CPU is so damn simple it would make a great state machine"
but I wasn't about to try to build one out of PALs and TTL...
And a year and a half later I find out that somebody else at another college
had the money and the connections to make a 65816 state machine.
I am very disappointed in WDC that they did not think of this first.
>In addition, WDC rates their processor speed by about 15 different timing
>relationships. They rate data and address input and output timing as well
>as the relationship between different clock and control signals. If any
>ONE of those timing specs does not work at a particular speed, then the
>chip is rated at a lower speed. WDC has chips that might run at 20 MHz
>(that's a guess on my part) in a custom circuit that is designed to work
>around the slower timing ratios. The fact is that the overall CPU speed
>is based on many factors, with the slowest measured timing being the limit.
No argument here, just don't see how it applies. The ASIC chip is a data
file which gets handed to a chip house and they use it to configure a
gate array they have already designed and tested. Fadell didn't specify
that the chip would run at 20 mhz, the chip house told him that his design
on their gate array would be able to run at 20 mhz with the necessary timing
ratios.
WDC's chips might run at 20 mhz -- if you have -10 ns SRAM. WDC's chips
are, bluntly put, sloppily designed compared to the ASIC gate array.
>A common misconception about integrated circuits is the assumption that
>there are different production runs for each chip speed. Actually, a chip
>manufacturer attempts to make every chip at top speed, and then tests the
>performance before marking them.
Well, that's true for each spread of speeds. Motorola makes two seperate
production runs for 8-20 mhz chips and for 33-50 mhz chips.
You're otherwise correct.
>>---hey Apple, wanna buy some chips?
>I hope they don't, unless they do extensive compatibility testing on them.
>At a time when Intel cannot get their own 80486 processors to run 8086
>code, I am very suspect of a chip that was designed by a single college
>kid.
So would I -- but the 65816 (both WDC and ASIC) is an 8000 gate design,
compared to the 400,000 gate 80486 (assuming 1 gate == 3 transistors on avg).
I agree with your requirement of extensive compatibility testing; however,
after looking at the 65816 data sheet I do not think that will be a problem.
>Don't forget that a 8 MHz 6502 is running like a 35 to 40 MHz 8088
>(although I can't say what speed 80486 it can compete with). Also, a
>10 MHz 65C816 can keep up with a 20 MHz 68000 (but I wouldn't put it
>up against a 68040). This is not considering video or disk I/O.
Barf! Cross CPU comparisons are generally meaningless. Comparing a IIGS at
2.5 mhz under GS/OS w/ Appleworks GS to a 12 mhz 286 under windows 2 with
Microsoft Works... _that_ means something.
Todd Whitesel
toddpw @ tybalt.caltech.edu
Stephen Brown
Really, Brian Willoughby's message is about the ASIC 65816.
>I found it hard to believe (and still do) that some college kid has done a
> better job all by himself than what the Western Design Centre can do
with
>a team of enginners. Now I'm not too surprised that his "20 Mhz" CPU has
>turned out to be 15 Mhz (which you will note is only about 2 Mhz faster
Oh boy! If you don't believe that 'some college kid' has done this, you can
read the Michigan State University's alumni newsletter for details. You'll
read that he didn't do this task all by himself. Some college kids can't
write. Others can. Why is it SO inconceivable that one particularly bright one
could co-design something really good? Got something against college students?
Bill Mensch may have been the chief designer of the 65816, but my
understanding is that his wife or daughter (or something) did the layout,
without CAD. His chip's design might be okay, but its far from optimum.
WDC's 62816's are experimental above 8 Mhz, and even the 8 Mhz ones are not
available in large quantity. ASIC's will be. WDC's 65816
chips will not run all instructions at full speed. ASIC's will. WDC's 65816
chips require 6 volts for the fast (experimental) ones. ASIC's take just 5, as
they should. Indeed, the fastest WDC 65816's are 13 Mhz, but so few are
available (due to poor yield) that they are still a freak of nature.
>The fact is that the overall CPU speed
>is based on many factors, with the slowest measured timing being the limit.
What ARE you talking about? If the CLOCK speed can run at xx Mhz, then it says
something about all aspects of the IC's timing. Other than having a chip that
has to slow down for some instructions, please tell me how a chip whose clock
runs at xx Mhz ISNT a xx Mhz chip...
You seem to have a blind faith in WDC. If you note, the ABORT instruction in
the 65816 does not work according to the way its supposed to. What about that
tidbit?
>>---hey Apple, wanna buy some chips?
>
>I hope they don't, unless they do extensive compatibility testing on them.
Do you think that they wouldn't?
>Don't forget that a 8 Mhz 6502 is running like a 35 to 40 Mhz 8088.
That's really interesting. And a bit hard to prove, and completely nonsense if
you look at benchmarks, eg. those that appear in Lichty and Eyes on the 65816.
>10 Mhz 65C816 can keep up with a 20 Mhz 68000 (but I wouldn't put it
up against a 68040). This is not considering video or disk I/O.
What??? The particular way that video or disk I/O is implemented is computer,
not CPU, specific. So please, don't consider video or disk I/O.
>Brian Willoughby
Why not contact ASIC, at (818) 597-9165 voice, or (818) 706-2178 fax, and ask
them. Why not get their interpretation of the facts before you hit the old red
alert? I don't have any connection with these guys. I do have a short fuse
however, when there are individuals who will flame for no reason
but ignorant cynicism.
Tae Song
>wife and daughter. The original 65816 mask was laid out BY HAND five
>years ago and they have NEVER tried using the state of the art gate array
>approach that Tony Fadell had the connections to gain access to.
The 65816 was done by Bill Mensch and his SISTER. Bill Mensch did the design
and his sister the lay out. All the design was done by Bill's hand (to mylar),
because 1) it added to cost of making the chip and 2) he doesn't believe in CAD
programs for some reason. His sister did the layout as was mentioned in a rare
interview several years ago in Compute magazine when the GS came out. Oh
correction I ment it saved money by doing it by hand.
On CPU comparisons... the 68000-68030 buffered the clock and produce an
internal clock... 1/2 the external clock speed. A 50Mhz 68030 is actually
running 25Mhz internally. The 68040 fame is that it doesn't do this, thus a
25Mhz is twice as fast 68030, straight out.
The 65816 could've been design to be faster, but been design by hand some logic
circuits needed was sacrificed. There's only 3 registers vs 16+ on the 680x0
and Ix86s. There's probablely other things as well...
s.
Brian WILLOUGHBY
>bri...@microsoft.UUCP (Brian WILLOUGHBY) writes:
>
>>I found it hard to believe (and still do) that some college kid has done a
>>better job all by himself than what the Western Design Center can do with
>
>WDC does not have "a team of engineers" -- they have Bill Mensch and his
>wife and daughter. The original 65816 mask was laid out BY HAND five
>years ago and they have NEVER tried using the state of the art gate array
>approach that Tony Fadell had the connections to gain access to.
So, you believe everything you read on the net? Just because of the
"net legend" of the Mensch family, you have extrapolated that there are
no other WDC employess? Someone at WDC did extensive research into the
interaction between the 65C8xx and the Apple Disk ][ card - has anyone
even powered up an Apple ][ with the ASIC chip in it? Before I get all
happy about my future computing possibilities, I'd like to hear a little
more about what is behind ASIC. Did you know that W.D.Mensch worked
for the company that originally designed the 6502? I think that
qualifies him to do design work in his kitchen after a decade of
experience. I hope you realize that WDC has MANY more customers than
Apple Co. They happen to be very popular in the medical industry and
with embedded controllers. WDC works with more than the Apple ][, but
the ASIC chip hasn't even done that yet!
>A couple years ago when I got my hands on the 65816 data sheet I took one
>look at the cycle-by-cycle bus state listing (all of two pages) and said
>"you know, this CPU is so damn simple it would make a great state machine"
>but I wasn't about to try to build one out of PALs and TTL...
>
>And a year and a half later I find out that somebody else at another college
>had the money and the connections to make a 65816 state machine.
>
>I am very disappointed in WDC that they did not think of this first.
Todd, I'm quite impressed with your knowledge of electronics, and I
enjoy hearing your ideas. But what I don't enjoy is your ragging on
a company when you have no idea what they did. I'll forgive you,
though, since this is obviously a religious issue :-)
How do you know that WDC *didn't* think of gate arrays? I've learned
that gate arrays are great for quick, space-efficient design of logic
circuits - but the tradeoff is slower operation. Hard-coded logic
takes longer to design, and requires custom fabrication, but the
resulting chip is generally faster. Gate arrays are quicker and
cheaper to fabricate, bacause they are all the same. There is no
difference between the ASIC 65C816 and some other chip - at least not
until the array is programmed for the specified circuit paths. I
would hardly say that gate array is the optimum design choice for a
processor. I suppose that we will find out, but I will wait for the
testing stage before I go counting my eggs.
>>In addition, WDC rates their processor speed by about 15 different timing
>>relationships. They rate data and address input and output timing as well
>>as the relationship between different clock and control signals. If any
>>ONE of those timing specs does not work at a particular speed, then the
>>chip is rated at a lower speed. WDC has chips that might run at 20 MHz
>>(that's a guess on my part) in a custom circuit that is designed to work
>>around the slower timing ratios. The fact is that the overall CPU speed
>>is based on many factors, with the slowest measured timing being the limit.
>
>No argument here, just don't see how it applies. The ASIC chip is a data
>file which gets handed to a chip house and they use it to configure a
>gate array they have already designed and tested. Fadell didn't specify
>that the chip would run at 20 mhz, the chip house told him that his design
>on their gate array would be able to run at 20 mhz with the necessary timing
>ratios.
It applies because WDC is qualifying their speed claims, but there is
no reference for the ASIC chips. What do they mean by 15 MHz? How can
a system (or an accelerator card) be designed to use the ASIC chip
around such an unqualified rating? I can be sure of what it means when
WDC says their chip runs at a certain speed. Without all the timing
specs, I don't trust the ASIC speed rating. I still haven't heard of
anyone plugging an ASIC chips into a modified TransWarp and actually
running Apple ][ software...
>WDC's chips might run at 20 mhz -- if you have -10 ns SRAM. WDC's chips
>are, bluntly put, sloppily designed compared to the ASIC gate array.
Do you really know anything about how the WDC chip was designed? Do
you know anything about how the ASIC chip is designed? How do you know
which is sloppy and which isn't? You seem to be making many statements
based purely on conjecture.
The ASIC chip would require the same speed SRAM as the WDC chip if they
were running at the same speed.
>>A common misconception about integrated circuits is the assumption that
>>there are different production runs for each chip speed. Actually, a chip
>>manufacturer attempts to make every chip at top speed, and then tests the
>>performance before marking them.
>
>Well, that's true for each spread of speeds. Motorola makes two seperate
>production runs for 8-20 mhz chips and for 33-50 mhz chips.
>You're otherwise correct.
True, there are different technologies being developed all the time.
Each successive fabrication technology is generally smaller and faster.
Motorola simply didn't shut down their old fabrication facilities
because they know that there is a market for the slower (cheaper) chips.
Here's an idea: perhaps WDC still produces 65C8xx's with medium speed
technology because the bulk of their customers (not Apple) only need a
certain amount of speed. Without the capitol investment, and without
the promise that there will be a merket, I can see how WDC might not
be using the fastest fabrication technology until Apple is willing to
commit. This is just a theorization on my part.
>>Don't forget that a 8 MHz 6502 is running like a 35 to 40 MHz 8088
>>(although I can't say what speed 80486 it can compete with). Also, a
>>10 MHz 65C816 can keep up with a 20 MHz 68000 (but I wouldn't put it
>>up against a 68040). This is not considering video or disk I/O.
>
>Barf! Cross CPU comparisons are generally meaningless. Comparing a IIGS at
>2.5 mhz under GS/OS w/ Appleworks GS to a 12 mhz 286 under windows 2 with
>Microsoft Works... _that_ means something.
Ok, I admit that such comparisons are not final, but I am just tired
of so many people assuming that the clock speed of different processors
are interchangeable. The point that I was making was that instead of
thinking that a 1 MHz 6502 is roughly equivalent to a 1 MHz PC (which
is way off), think of it as a 5 MHz PC (which isn't precise, but is
much closer to realistic). My gripe is that 20 MHz seems to be a
goal that everyone on the net wants the ASIC chips to reach, and I
think that this is based on 20 MHz PC performance. I just want to get
that sort of comparison out of people's heads. There is much more to
computer performance than a couple of numbers.
>Todd Whitesel
>toddpw @ tybalt.caltech.edu
Brian Willoughby
Todd P. Whitesel
[ in response to stuff I wrote about WDC ]
>So, you believe everything you read on the net? Just because of the
>"net legend" of the Mensch family, you have extrapolated that there are
>no other WDC employess?
No, I was only discrediting someone's idea that "a team of engineers" designed
the 65816. Bill Mensch did a good job on the instruction set, but his mask
leaves a lot to be desired since it does not lend itself to high speed
operation. Unless they've fixed things, on the 8 mhz parts REP and SEP take
250 ns to operate so you have to put a NOP after each one OR you have to
stretch the clock the way the transwarp does. WDC has admitted that this is
caused by very long signal lines.
> Someone at WDC did extensive research into the
>interaction between the 65C8xx and the Apple Disk ][ card - has anyone
>even powered up an Apple ][ with the ASIC chip in it?
Not that I know of, because the ASIC chip is still at the fab house being made
into its first run. By the way, Jim Sather figured out that little trick of the
Disk ][ some time ago (see Understanding the Apple //e, I haven't seen his book
on the ][+). All it means is that the Disk ][ card requires a certain dead bus
cycle in order to operate; accelerators that use dead bus cycles for something
else would not work properly with the Disk ][ card itself. (What about the IWM)
> Before I get all happy about my future computing possibilities, I'd like to
>hear a little more about what is behind ASIC. Did you know that W.D.Mensch
>worked for the company that originally designed the 6502? I think that
>qualifies him to do design work in his kitchen after a decade of experience.
I'm not arguing with that, in fact it's one reason I admire his architectural
enhancements in the 65816. All I'm saying is that his timing margins are lousy
because of it. I am actually building stuff that uses his chips so I have to
know about this. The project I am building now will require wait states on the
DRAM, not because the DRAM is too slow, but because the WDC chip's timing
margins are very bad. (For a 4 mhz WDC chip you need 8 mhz'able parts, and
WDC's timing margins are forcing me to (a) make my timing generator a lot
more complex or (b) add a wait state. I decided to make the best of it and
perform a hidden refresh during the wait state.)
>I hope you realize that WDC has MANY more customers than
>Apple Co. They happen to be very popular in the medical industry and
>with embedded controllers. WDC works with more than the Apple ][, but
>the ASIC chip hasn't even done that yet!
I agree here. My point is that for high speed designs WDC has not delivered.
ASIC is using an extremely obvious approach that WDC should have used _IF_
they really wanted high speed 65816's. Many of WDC's markets are not very
high speed (40 khz medical controllers, for example) and with Apple's
past attitude I can't blame WDC for not sinking a lot of resources into a
new gate array design.
>what I don't enjoy is your ragging on a company when you have no idea what
>they did. I'll forgive you, though, since this is obviously a
>religious issue :-)
No idea? What they did is produce a mask that works but has been giving them
gobs of trouble when they try to shrink it. I will stop ragging on them IF
they can get into production a part that:
runs at 15 Mhz (14.31818 or better, really) w/ 35 ns SRAMs
is available in single quantities _somewhere_ for reasonable $$$
does not have the blasted REP/SEP timing problem
handles ABORT in a usable way (it doesn't currently)
What I am ragging on is the fact that they are trying to milk more speed out
of the same mask when it would be a lot easier to redesign the mask itself so
it is native to a newer technology that does run at higher speeds.
ASIC reverse-engineered the chip from WDC's timing diagrams. Their utmost goal
is "105% compatibility" meaning that all software will work (even the Disk ][)
and that the REP/SEP quirks will be gone. They might have fixed ABORT, but I
don't know for sure.
>How do you know that WDC *didn't* think of gate arrays?
They *thought* about it, but didn't actually do it. Mensch said on America
Online last year that 100 Mhz GaAs gate arrays were large enough to hold the
65816 logic diagram and that he was looking into it.
> I've learned that gate arrays are great for quick, space-efficient design of
>logic circuits - but the tradeoff is slower operation. Hard-coded logic takes
>longer to design, and requires custom fabrication, but the resulting chip is
>generally faster. Gate arrays are quicker and cheaper to fabricate, bacause
>they are all the same.
That used to be the case (IOU & MMU from the //e, for example), but gate arrays
were so popular that speeding them up became a significant area of research.
The ASIC chip is made possible by the fruits of that research. Gate arrays are
now fast enough (and big enough for an 8000 gate design like the 65816); they
are also cheaper to make and are very easy to second source... in other words,
Apple loves them. If the ASIC chip really is 100% compatible then Apple will
jump on it. (They'd better...)
BTW, Apple has had the tools to do what ASIC is doing for a few years now.
Look at a recent Mac II motherboard if you doubt me.
> There is no difference between the ASIC 65C816 and some other chip - at least
>not until the array is programmed for the specified circuit paths. I would
>hardly say that gate array is the optimum design choice for a processor. I
>suppose that we will find out, but I will wait for the testing stage before I
>go counting my eggs.
I agree with your prudence; I am not in the least bit worried because I've seen
the software that is used to design and test these things *before* any chips
are actually fabricated. You wouldn't believe how sophisticated the tools are.
Main problem is the setup cost; big design companies can afford it but WDC
probably can't. ASIC's Tony Fadell had industry connections, without which he
would never have been able to afford the cost.
>WDC is qualifying their speed claims, but there is
>no reference for the ASIC chips. What do they mean by 15 MHz? How can
>a system (or an accelerator card) be designed to use the ASIC chip
>around such an unqualified rating? I can be sure of what it means when
>WDC says their chip runs at a certain speed. Without all the timing
>specs, I don't trust the ASIC speed rating. I still haven't heard of
>anyone plugging an ASIC chips into a modified TransWarp and actually
>running Apple ][ software...
All good arguments; here's why they don't bother me. ASIC has claimed from
the start that they will be fully compatible with the PLCC version of WDC's
chip. This means they will have to at least respect the timing margins given
by WDC. From my examination of WDC data sheets I do not think that will
be very hard to do.
[ my comment about WDC's chip running at 20 mhz with -10 ns SRAM deleted ]
>Do you really know anything about how the WDC chip was designed? Do
>you know anything about how the ASIC chip is designed? How do you know
>which is sloppy and which isn't? You seem to be making many statements
>based purely on conjecture.
No, they're based on bits of information gleaned from data sheets and
interviews, and as to how the ASIC chip is designed, from news articles and
my own experience with industrial CAD systems.
>The ASIC chip would require the same speed SRAM as the WDC chip if they
>were running at the same speed.
You don't know that any more than I do. It largely depends on the base array
they are using. My guess is that they are staying happy with 'same speed' for
everything for now -- they can always use a faster base array when they want
to run faster or use slower SRAM -- to keep costs down.
>Here's an idea: perhaps WDC still produces 65C8xx's with medium speed
>technology because the bulk of their customers (not Apple) only need a
>certain amount of speed. Without the capitol investment, and without
>the promise that there will be a merket, I can see how WDC might not
>be using the fastest fabrication technology until Apple is willing to
>commit. This is just a theorization on my part.
Makes sense to me. Mensch had big plans a few years ago; but according to
their own people, the 65832 is on hold until a customer wants them to make it.
[ stuff about meaningless clock speed comparisons deleted ]
> My gripe is that 20 MHz seems to be a goal that everyone on the net wants
>the ASIC chips to reach, and I think that this is based on 20 MHz PC
>performance. I just want to get that sort of comparison out of people's
>heads. There is much more to computer performance than a couple of numbers.
My source for the 20 mhz figure is an interview on America Online in which
Tony Fadell said that the _fab_house_ told him the chips would "run at 21 mhz
or they would replace them for free." I can dig up the interview and post it
if you're interested.
I guess my real beef agaist WDC is that they appear to be dealing with the
lack of high speed chips very inadequately, by milking the original technology
when a newer one should give better results. I can understand if it is
economically infeasible to do so, but they ought to TELL APPLE THAT rather than
blowing off steam at AppleFest. Just saying "we can ship if you order" won't
convince Apple, you have to tell them "we can ship x chips per month from these
sources, with all parts tested to such&such specification" and I haven't seen
WDC doing that.
Brian WILLOUGHBY
>In-Reply-To: message from bri...@microsoft.UUCP
>
>Really, Brian Willoughby's message is about the ASIC 65816.
>
>>I found it hard to believe (and still do) that some college kid has done a
>> better job all by himself than what the Western Design Centre can do
>with
>>a team of enginners. Now I'm not too surprised that his "20 Mhz" CPU has
>>turned out to be 15 Mhz (which you will note is only about 2 Mhz faster
>
>Oh boy! If you don't believe that 'some college kid' has done this, you can
>read the Michigan State University's alumni newsletter for details. You'll
>read that he didn't do this task all by himself. Some college kids can't
>write. Others can. Why is it SO inconceivable that one particularly bright one
>could co-design something really good? Got something against college students?
Whoa, don't make too many assumptions there. I have a BSEE, so I
have some faith in college students. But I also happen to have
experience in real-world electronic design. I've done more than
read about the WDC chips in some alumni paper - I have been using
them for four years! (along with NCR and Rockwell 65C02 clones)
I have not yet had the opportunity to personally fondle one of the
ASIC chips, nor have I heard of anyone who has (they could probably
be arrested for that anyway :-)
>Bill Mensch may have been the chief designer of the 65816, but my
>understanding is that his wife or daughter (or something) did the layout,
>without CAD. His chip's design might be okay, but its far from optimum.
Oh, I think I understand: women have no electronic design abilities
and all humans are less capable than CAD systems?
First of all, I don't know that I believe that rumor, but it is
entirely possible that Mrs. or Ms. Mensch knew what she was doing.
Also, you seem to think that nothing can be done without CAD, and
you seem to rate CAD software above human design abilities. In my
experience, some designs are much better when done by humans,
especially compared to the performance of PC based CAD systems
(which are extremely primitive). If ASIC used the typical
university available CAD software, then their design is far from
optimum. In 1988 when I was in college, it was a well known fact
(the professors warned us) that the student oriented mainframe CAD
software was far from professional standards.
The worst you could do by proving such a story is bring the design
of the WDC chip down to the amateur/garage/kitchen level that the
ASIC team used and I would still favor the design that has been
proven to work. Let me get my hands on some ASIC product!
>WDC's 62816's are experimental above 8 Mhz,
Not true, I have a 10 MHz 65C802 that is a year old.
>, and even the 8 Mhz ones are not
>available in large quantity. ASIC's will be.
Until it happens, I wouldn't be so quick to trust ASIC to do what
WDC (a company with many customers besides just Apple and AE)
has had difficulty doing. If the investment isn't there, the
chips cannot be made. Looking back in computer history, IBM
decided to use the 8086 over the 68000 simply because Motorola
could not promise to deliver sufficient quantities. I think one
college student will run into similar difficulties.
>. WDC's 65816
>chips will not run all instructions at full speed. ASIC's will.
How do you know that ASIC will run all instructions at full speed?
We know the shortcomings of the WDC chip because it is available -
the ASIC chip hasn't been tested in real world systems yet.
>. WDC's 65816
>chips require 6 volts for the fast (experimental) ones. ASIC's take just 5, as
>they should.
If you knew the gory details of integrated circuit electronics,
the 6 volt "kludge" would make a little more sense. I'll hold off
judgement until the ASIC has been tested.
>. Indeed, the fastest WDC 65816's are 13 Mhz, but so few are
>available (due to poor yield) that they are still a freak of nature.
But you are assuming that the laws of nature will bend for ASIC?
As I stated in an earlier posting, gate array logic is generally
SLOWER than hard-coded logic. The main advantage is quick design
time and fabrication of multiple designs with a common wafer.
>>The fact is that the overall CPU speed
>>is based on many factors, with the slowest measured timing being the limit.
>
>What ARE you talking about? If the CLOCK speed can run at xx Mhz, then it says
>something about all aspects of the IC's timing. Other than having a chip that
>has to slow down for some instructions, please tell me how a chip whose clock
>runs at xx Mhz ISNT a xx Mhz chip...
Boy, you ask hard questions. My first response was that it would
be nearly impossible to explain such things to a layman without
first requiring a 4 year degree in EE.
But I'll give you an example:
As we all know, the Apple //e and most of the //c's are clocked at
1 MHz, right? Why don't you tell me why Apple Co. needed to put a
2 MHz processor in all of these systems? That's because even though
the clock was only running at 1 MHz, the other digital signals
(address and data, etc) had to be able to change values very fast to
deal with the MMU and IOU.
Of course, this is an example where the system was at fault, and not
the processor, but I think you see that the problem is much more
than one dimensional, even though the average layman would like to
think that it is.
WDC has entire debugging systems (based on the Apple //, of course)
to test the interaction between their processors and the target
system. Such testing concerns are no simple matter.
>You seem to have a blind faith in WDC.
Just the opposite: my "faith" in WDC extends only so far as I have
witnessed the performance of their products. The general trend of
this group has been, in my opinion, based too much on "faith" in
the ASIC project - of which I have seen no product. Wild
assumptions have been made by some - most of which were not based
on sound electronics engineering priciples - and this has, in turn,
caused many people to hold what I feel is a false hope in a 20 MHz
Apple compatible.
>. If you note, the ABORT instruction in
>the 65816 does not work according to the way its supposed to. What about that
>tidbit?
I'm aware of many of the flaws in the WDC chips. I had a 65C802
in 1986 which was a bit flaky with interrupts. And as a result of
those bugs, I was on the phone with WDC engineers who had extensive
knowledge of how their chips worked in the Apple ][. BTW, the
engineers name was not Bill Mensch, so I know they have a few people
there. But my point is that the WDC chips are subject to criticism
simply because they are available and currently being used in
systems. Who knows what "tidbits" will appear when the ASIC chip is
put to the test?
>>>---hey Apple, wanna buy some chips?
>>
>>I hope they don't, unless they do extensive compatibility testing on them.
>
>Do you think that they wouldn't?
Of course they would, but I'm not going to try to choose between
ASIC and WDC *before* these tests are run. And I really doubt that
Apple or AE have decided to invest in ASIC just yet.
>>Don't forget that a 8 Mhz 6502 is running like a 35 to 40 Mhz 8088.
>
>That's really interesting. And a bit hard to prove, and completely nonsense if
>you look at benchmarks, eg. those that appear in Lichty and Eyes on the 65816.
Thanks for the reference, I'll have to read that.
You must remember that, at a given clock speed, an 80486 blows away
an 80386 which in turn blows away everything before it (except that
there are a few instructions which the 80386 executes slower than an
80286). So I am not making such an outrageous claim about the 6502
vs. the 8088.
>>10 Mhz 65C816 can keep up with a 20 Mhz 68000 (but I wouldn't put it
>up against a 68040). This is not considering video or disk I/O.
>
>What??? The particular way that video or disk I/O is implemented is computer,
>not CPU, specific. So please, don't consider video or disk I/O.
In terms of the Apple ][, one must consider I/O because that is the
major limiting factor in an Apple - even one with a TransWarp.
>Why not contact ASIC, at (818) 597-9165 voice, or (818) 706-2178 fax, and ask
>them. Why not get their interpretation of the facts before you hit the old red
>alert? I don't have any connection with these guys. I do have a short fuse
>however, when there are individuals who will flame for no reason
>but ignorant cynicism.
Thanks for thier number. That's much more than I had previously.
I have hit no such "red alert", I'm merely grabbing the reins on a
team of runaway horses who don't know where to stop when they get
the faintest hint of "go". All I am saying is that you hold your
anti-WDC flames until after ASIC has proven themselves. My mail
was not a flame, but a response to flames against WDC.
Todd P. Whitesel
>As I stated in an earlier posting, gate array logic is generally
>SLOWER than hard-coded logic. The main advantage is quick design
>time and fabrication of multiple designs with a common wafer.
How old is your information? I've seen gate array data books and things aren't
anywhere near as bad as you claim. The Mac II series has been disproving your
"statement" for a few years now...
> Wild assumptions have been made by some - most of which were not based
>on sound electronics engineering priciples - and this has, in turn,
>caused many people to hold what I feel is a false hope in a 20 MHz
>Apple compatible.
I give up. Wait until the first samples are out in a few weeks and convince
yourself. Your experience is totally removed from the development tools ASIC
has insider access to. ASIC is not getting anywhere because they are two
college students, they are getting somewhere because they know the right
people and can gain access to considerably bigger guns than you are giving
them credit.
Brian WILLOUGHBY
>
>>As I stated in an earlier posting, gate array logic is generally
>>SLOWER than hard-coded logic. The main advantage is quick design
>>time and fabrication of multiple designs with a common wafer.
>
>How old is your information? I've seen gate array data books and things aren't
>anywhere near as bad as you claim. The Mac II series has been disproving your
>"statement" for a few years now...
I hate to say it, but Mac II technology has never been state of the
art. The 16 MHz Mac II had 2 wait states even though 16 MHz was
hardly fast for a 68020 machine of that time. The 25 MHz IIci was
also not the fastest machine of its day. The newer 40 MHz IIfx seems
to be a bit more competitive, but I don't know how fast Apple's
competition is running this year.
My point is that the Mac II can afford to use the cheaper, space
efficient, easily-designed gate array approach because they are not
state of the art in terms of high performance speed. Apple Co. uses
this technology with severe tradeoffs.
>> Wild assumptions have been made by some - most of which were not based
>>on sound electronics engineering priciples - and this has, in turn,
>>caused many people to hold what I feel is a false hope in a 20 MHz
>>Apple compatible.
>
>I give up. Wait until the first samples are out in a few weeks and convince
>yourself. Your experience is totally removed from the development tools ASIC
>has insider access to. ASIC is not getting anywhere because they are two
>college students, they are getting somewhere because they know the right
>people and can gain access to considerably bigger guns than you are giving
>them credit.
Actually, I am familiar with the tools they are using - I'm just
surprised that WDC hasn't tried similar approaches. If a college
budget can afford it, then why hasn't WDC hired a college student
to experiment with such designs before now? Perhaps I should ask
this question of WDC!
I hope ASIC will make their chips available at a resonable
cost/quantity. I would like to experiment "in a few weeks".
Anyway, I wish good luck to ASIC. Even if they don't meet their
goal, they might bring a little healthy competition to the 65C816
market.
P.S. Are there any other sources of the 65C816? What speed?
Doug Gwyn
The one that came with my IIGS was made by GTE (3MHz, although I've seen
4MHz versions in photos of IIGS motherboards). I don't know if this is
simply the WDC mask being manufactured under license or what.
Todd P. Whitesel
>Actually, I am familiar with the tools they are using - I'm just
>surprised that WDC hasn't tried similar approaches. If a college
>budget can afford it, then why hasn't WDC hired a college student
>to experiment with such designs before now? Perhaps I should ask
>this question of WDC!
A college budget COULDN'T afford it. The only reason ASIC has gotten this
far is because they knew people who got them cheap time on the CAD systems.
I would still ask this question of WDC. I am sick and tired of lousy high
speed yields and an asinine $100 minimum order. I haven't been able to find
65816's available anywhere else (JameCo doesn't carry them any more) and WDC
is acting like they don't really want our business.
Chris Wicklein
The following is based on various peoples impressions after using an Apple
IIGS vs. a typical IBM PC class machine (but thats what really counts):
Take the speed of a 65C816 chip, multiply it by about 3.75, and that is the
approx. MHz rating of an equal 8088 family chip.
------------Chris Wicklein----------crew@pro-harvest------------------------
Jay Giurleo
>
> Take the speed of a 65C816 chip, multiply it by about 3.75, and that is the
>approx. MHz rating of an equal 8088 family chip.
While it is true that even the 8088 series is faster than the GS, you
really can't multiply the clock speeds of two completely different processors
and get a reliable speed comparison. By the way, the unaccelerated 8088
ran at 4.77 MHz.
--
---------------------------------------------------------------------------
Schmidts Law: If you mess with a thing long enough, it'll break.
---------------- Jay Giurleo ---------------- ja...@wpi.wpi.edu ------------
Doug Gwyn
>In article <8149.apple.net.info-apple@pro-harvest> cr...@pro-harvest.cts.com (Chris Wicklein) writes:
>> Take the speed of a 65C816 chip, multiply it by about 3.75, and that is the
>>approx. MHz rating of an equal 8088 family chip.
> While it is true that even the 8088 series is faster than the GS, you
>really can't multiply the clock speeds of two completely different processors
>and get a reliable speed comparison. By the way, the unaccelerated 8088
>ran at 4.77 MHz.
To the contrary, Chris was claiming that the 8088 was a factor of
3.75 times SLOWER than the 65816, and my own observations back his
estimate. Note that he was trying to give you a "rule of thumb"
for comparing the OVERALL performance of such systems, given that
you knew the clock rates. Thus to match a TWGS-equipped IIGS
running at 7MHz you would need an 8088-family processor running
around 26.25MHz. Of course, it does depend on the nature of your
applications.