Well, that could be part of the problem. The DMAC and the RAMSEY are a
matched set. If you have Rev 1/2 DMAC, you should have Rev 4 RAMSEY,
and if you have Rev 4 DMAC, you need Rev 7 RAMSEY.
I don't know all the details, but it all stems from the fact that
RAMSEY is the address generator during DMA transfers (that's how you
get 32 address/32 data, plus I/O and control connections, using 84-pin
chips). The DMAC starts to run a transfer, RAMSEY counts, without
being told what to count, it's implicit in the transfer. Only, the
older chipset only supported longword-aligned transfers (usually, but
not always, what you get), the new chipset supports word aligned
transfers.
Dave Haynie | ex-Commodore Engineering | See my first film
Sr. Systems Engineer | Class of '94 | "The Deathbed Vigil"
Scala Inc., US R&D | C= Failure n. See: Greed | in...@iam.com
"Caught a bolt of lightning, cursed the day he let it go" -Pearl Jam